replaced dp_fifo_dc with dp_fifo_dc_arr

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -18,7 +18,7 @@
 --
 -------------------------------------------------------------------------------
 
--- Authors : J Hargreaves, L Hiemstra
+-- Authors : J Hargreaves, L Hiemstra, R van der Walle
 -- Purpose:  
 --   AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
 -- Description:
@@ -124,7 +124,6 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
   SIGNAL rx_rst                     : STD_LOGIC; 
   SIGNAL rx_sysref                  : STD_LOGIC; 
 
-  SIGNAL arst                       : STD_LOGIC;
   SIGNAL rx_bsn_source_restart      : STD_LOGIC;
 
   -- Sosis and sosi arrays
@@ -447,47 +446,31 @@ BEGIN
   -- Output Stage
   --   . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
   -----------------------------------------------------------------------------
- 
-  gen_dp_fifo_dc : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
-    u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
-      GENERIC MAP (
-        g_data_w         => c_sdp_W_adc_jesd,
-        g_bsn_w          => c_bs_bsn_w,
-        g_use_empty      => FALSE, --TRUE,
-        g_use_ctrl       => TRUE,
-        g_use_sync       => TRUE,
-        g_use_bsn        => TRUE,
-        g_fifo_size      => c_dp_fifo_dc_size
-      )
-      PORT MAP (
-        wr_rst           => rx_rst,
-        wr_clk           => rx_clk,
-        rd_rst           => dp_rst,
-        rd_clk           => dp_clk,
-        snk_in           => st_sosi_arr(I),
-        src_out          => out_sosi_arr(I)
-      );
-  END GENERATE;
-
-  -- use common dc fifo for restart signal
-  u_common_fifo_dc_restart : ENTITY common_lib.common_fifo_dc
-  GENERIC MAP (
-    g_dat_w     => 1,
-    g_nof_words => c_dp_fifo_dc_size
-  )
-  PORT MAP (
-    rst     => arst,
-    wr_clk  => rx_clk,
-    wr_dat(0)  => rx_bsn_source_restart,
-    wr_req  => bs_sosi.valid,
-    rd_clk  => dp_clk,
-    rd_dat(0)  => dp_bsn_source_restart,
-    rd_req  => '1'
-  );
-
-  arst <= rx_rst OR dp_rst;
+  u_dp_fifo_dc_arr : ENTITY dp_lib.dp_fifo_dc_arr
+    GENERIC MAP (
+      g_nof_streams    => c_sdp_S_pn,
+      g_data_w         => c_sdp_W_adc_jesd,
+      g_bsn_w          => c_bs_bsn_w,
+      g_use_empty      => FALSE,
+      g_use_ctrl       => TRUE,
+      g_use_sync       => TRUE,
+      g_use_bsn        => TRUE,
+      g_use_aux        => TRUE,
+      g_fifo_size      => c_dp_fifo_dc_size
+    )
+    PORT MAP (
+      wr_rst           => rx_rst,
+      wr_clk           => rx_clk,
+      rd_rst           => dp_rst,
+      rd_clk           => dp_clk,
+      snk_in_arr       => st_sosi_arr,
+      src_out_arr      => out_sosi_arr,
+      in_aux(0)        => rx_bsn_source_restart,
+      out_aux(0)       => dp_bsn_source_restart
+    );
 
-  -----------------------------------------------------------------------------
+  
+-----------------------------------------------------------------------------
   -- JESD Control register
   -----------------------------------------------------------------------------
   u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w