Monitor FIFO fill level.

libraries/io/eth/src/vhdl/eth_tester_rx.vhd

@@ -74,6 +74,8 @@ ARCHITECTURE str OF eth_tester_rx IS
   SIGNAL rx_fifo_siso        : t_dp_siso;
   SIGNAL rx_fifo_sosi        : t_dp_sosi;
   SIGNAL rx_fifo_data        : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+  SIGNAL rx_fifo_wr_ful      : STD_LOGIC;
+  SIGNAL rx_fifo_usedw       : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0);
   SIGNAL unpacked_sosi       : t_dp_sosi;
   SIGNAL unpacked_data       : STD_LOGIC_VECTOR(c_octet_w-1 DOWNTO 0);
   SIGNAL crc_corrupt         : STD_LOGIC := '0';
@@ -145,6 +147,9 @@ BEGIN
   PORT MAP (
     rst         => st_rst,
     clk         => st_clk,
+    -- Monitor FIFO filling
+    wr_ful      => rx_fifo_wr_ful,
+    usedw       => rx_fifo_usedw,
     -- ST sink
     snk_in      => decoded_sosi,
     -- ST source