Merge branch 'L2SDP-180' into 'master'

Resolve L2SDP-180

Closes L2SDP-180

See merge request desp/hdl!59

libraries/base/common/hdllib.cfg

@@ -128,6 +128,9 @@ synth_files =
     src/vhdl/common_bit_delay.vhd
     src/vhdl/common_delay.vhd
     src/vhdl/common_shiftram.vhd
+
+    src/vhdl/common_variable_delay.vhd
+    src/vhdl/mms_common_variable_delay.vhd
     
     src/vhdl/mms_common_reg.vhd
     src/vhdl/mms_common_stable_monitor.vhd
@@ -186,6 +189,8 @@ test_bench_files =
     tb/vhdl/tb_common_transpose.vhd
     tb/vhdl/tb_common_transpose_symbol.vhd
     tb/vhdl/tb_common_zip.vhd
+    tb/vhdl/tb_common_variable_delay.vhd
+    tb/vhdl/tb_mms_common_variable_delay.vhd
     tb/vhdl/tb_requantize.vhd
     tb/vhdl/tb_resize.vhd
     tb/vhdl/tb_round.vhd
@@ -212,6 +217,7 @@ regression_test_vhdl =
     tb/vhdl/tb_common_shiftram.vhd
     tb/vhdl/tb_common_shiftreg.vhd
     tb/vhdl/tb_common_transpose_symbol.vhd
+    tb/vhdl/tb_common_variable_delay.vhd
     tb/vhdl/tb_resize.vhd
     #tb/vhdl/tb_round.vhd           -- has no self verification yet
     tb/vhdl/tb_requantize.vhd

libraries/base/common/src/vhdl/common_variable_delay.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Pieter Donker
+-- Purpose:
+-- . Delay input pulse by number of given delay cycles
+-- Description:
+-- . delay input pulse by delay number of cycles
+-- . output pulse is derived from low-high transition of input pulse.
+-- . the actual pulse delay will be delay + 1, due to implementation latency of 1 clk cycle
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.common_pkg.ALL;
+
+ENTITY common_variable_delay IS
+  GENERIC (
+    g_max_delay : NATURAL := 200 * 10**6
+  );
+  PORT (
+    rst        : IN  STD_LOGIC;
+    clk        : IN  STD_LOGIC;
+
+    delay      : IN  NATURAL RANGE 0 TO g_max_delay := 0;
+    enable     : IN  STD_LOGIC := '0';
+    in_val     : IN  STD_LOGIC;
+    out_val    : OUT STD_LOGIC
+  );
+END common_variable_delay;
+
+ARCHITECTURE rtl OF common_variable_delay IS
+
+  SIGNAL i_out_val       : STD_LOGIC;
+  SIGNAL nxt_out_val     : STD_LOGIC;
+  SIGNAL delay_cnt       : NATURAL;
+  SIGNAL nxt_delay_cnt   : NATURAL;
+  SIGNAL prev_in_val     : STD_LOGIC;
+
+BEGIN
+  out_val <= i_out_val;
+  
+  p_delay: PROCESS(enable, in_val, prev_in_val, delay, delay_cnt)
+  BEGIN
+    nxt_out_val   <= '0';
+    nxt_delay_cnt <= 0; 
+    
+    IF enable = '1' THEN
+      IF in_val = '1' AND prev_in_val = '0' THEN  -- detect rising edge of in_val
+        IF delay = 0 THEN
+          nxt_out_val <= '1';
+        END IF;
+      ELSE
+        nxt_delay_cnt <= delay_cnt + 1;
+        IF delay_cnt+1 = delay THEN
+          nxt_out_val <= '1';
+        END IF;
+      END IF;  
+    END IF;
+  END PROCESS; 
+
+  p_clk : PROCESS(rst, clk)
+  BEGIN
+    IF rst = '1' THEN
+      i_out_val   <= '0';
+      delay_cnt   <= 0;
+      prev_in_val <= '0';
+    ELSIF rising_edge(clk) THEN
+      i_out_val   <= nxt_out_val;
+      delay_cnt   <= nxt_delay_cnt;
+      prev_in_val <= in_val;
+    END IF;
+  END PROCESS;
+
+END rtl;

libraries/base/common/src/vhdl/mms_common_variable_delay.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Pieter Donker
+-- Purpose:
+-- . mm interface for common_variable_delay.vhd to enable output
+-- Description:
+-- . see common_variable_delay.vhd
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE work.common_pkg.ALL;
+USE work.common_mem_pkg.ALL;
+
+ENTITY mms_common_variable_delay IS
+  PORT (
+    mm_rst          : IN  STD_LOGIC;
+    mm_clk          : IN  STD_LOGIC;
+    dp_rst          : IN  STD_LOGIC := '0';
+    dp_clk          : IN  STD_LOGIC;
+
+    -- MM interface
+    reg_enable_mosi : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_enable_miso : OUT t_mem_miso;
+
+    delay           : IN  NATURAL := 0;
+    trigger         : IN  STD_LOGIC := '0';
+    trigger_dly     : OUT STD_LOGIC
+  );
+END mms_common_variable_delay;
+
+
+ARCHITECTURE rtl OF mms_common_variable_delay IS
+  
+  CONSTANT c_enable_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 1, 1, '0');
+  
+  SIGNAL enable_reg : STD_LOGIC_VECTOR(c_enable_mem_reg.dat_w*c_enable_mem_reg.nof_dat-1 DOWNTO 0);
+
+  SIGNAL enable : STD_LOGIC := '0';
+
+BEGIN
+  enable <= sl(enable_reg);
+  
+  -- device under test
+  u_dut : ENTITY work.common_variable_delay
+  PORT MAP (
+    rst     => dp_rst,
+    clk     => dp_clk,
+
+    delay   => delay,
+    enable  => enable,
+    in_val  => trigger,
+    out_val => trigger_dly
+  );
+
+  u_mms_common_reg : ENTITY work.mms_common_reg
+  GENERIC MAP (
+    g_mm_reg       => c_enable_mem_reg
+  )
+  PORT MAP (
+    mm_rst         => mm_rst,
+    mm_clk         => mm_clk,
+    st_rst         => dp_rst,
+    st_clk         => dp_clk,
+
+    reg_mosi       => reg_enable_mosi,
+    reg_miso       => reg_enable_miso,
+
+    in_reg         => enable_reg,
+    out_reg        => enable_reg   
+  );
+
+END;
\ No newline at end of file

libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Pieter Donker
+-- Purpose:
+-- . test bench for common_variable_delay.vhd
+-- Description:
+-- . see common_variable_delay
+-- --------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE work.common_pkg.ALL;
+USE work.common_str_pkg.ALL;
+USE work.tb_common_pkg.ALL;
+
+ENTITY tb_common_variable_delay IS
+END tb_common_variable_delay;
+
+ARCHITECTURE tb OF tb_common_variable_delay IS
+
+  CONSTANT c_clk_period       : TIME    := 10 ns;
+  CONSTANT c_trigger_interval : NATURAL := 40;  -- in clk's
+  CONSTANT c_trigger_latency  : NATURAL := 1;  -- in clk's
+  CONSTANT c_delay_arr        : t_natural_arr(0 TO 3) := (0, 1, 3, 12);
+  
+  SIGNAL tb_end : STD_LOGIC := '0';
+  SIGNAL rst    : STD_LOGIC;
+  SIGNAL clk    : STD_LOGIC := '0';
+  
+  SIGNAL delay       : NATURAL   := 0;
+  SIGNAL enable      : STD_LOGIC := '0';
+  SIGNAL trigger     : STD_LOGIC := '0';
+  SIGNAL trigger_dly : STD_LOGIC := '0';
+BEGIN
+
+  clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+  rst <= '1', '0' AFTER c_clk_period*4;
+
+  -- generate trigger signal
+  proc_common_gen_pulse(c_trigger_interval/2, c_trigger_interval, '1', rst, clk, trigger);
+
+  p_in_stimuli : PROCESS
+  VARIABLE clk_cnt : NATURAL := 0;
+  BEGIN
+    delay  <= 0;
+    enable <= '0';
+    
+    WAIT UNTIL rst = '0';
+    WAIT UNTIL rising_edge(clk);
+    
+    -- If enable = 0, no trigger_dly is expected, see wave-window
+    proc_common_wait_some_cycles(clk, 50);
+
+    
+    enable <= '1';
+    -- enable trigger output and count clk's between trigger lo-hi and trigger_dly lo-hi
+    -- check if counted clk's = c_trigger_latency + delay 
+    FOR i IN c_delay_arr'RANGE LOOP
+      delay <= c_delay_arr(i);
+      clk_cnt := 0;
+      proc_common_wait_until_lo_hi(clk, trigger);
+      WHILE trigger_dly = '0' LOOP
+        clk_cnt := clk_cnt + 1;
+        proc_common_wait_some_cycles(clk, 1);
+      END LOOP;
+      ASSERT clk_cnt = c_trigger_latency + delay REPORT "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency+delay) SEVERITY ERROR; 
+      proc_common_wait_some_cycles(clk, 10);
+    END LOOP;
+    
+    enable <= '0';
+    proc_common_wait_some_cycles(clk, 10);
+
+
+    tb_end <= '1';    
+    WAIT;
+  END PROCESS;
+
+  -- device under test
+  u_dut : ENTITY work.common_variable_delay
+  PORT MAP (
+    rst     => rst,
+    clk     => clk,
+
+    delay   => delay,
+    enable  => enable,
+    in_val  => trigger,
+    out_val => trigger_dly
+  );
+      
+END tb;
+
+

libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Pieter Donker
+-- Purpose:
+-- . test bench for mms_common_variable_delay.vhd to test enable by signal mm interface
+-- Description:
+-- . see common_variable_delay.vhd
+-- . Only verifies mm control of enable.
+-- . Detailde verification of trigger has been done already in tb_common_variable_delay.vhd.
+-- . Here it is sufficient to use Wave window to view effect of enable on trigger.
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE work.common_pkg.ALL;
+USE work.common_str_pkg.ALL;
+USE work.tb_common_pkg.ALL;
+USE work.common_mem_pkg.ALL;
+USE work.tb_common_mem_pkg.ALL; 
+
+ENTITY tb_mms_common_variable_delay IS
+END tb_mms_common_variable_delay;
+
+ARCHITECTURE tb OF tb_mms_common_variable_delay IS
+  CONSTANT c_clk_period       : TIME    := 10 ns;
+  CONSTANT c_trigger_interval : NATURAL := 40;  -- in clk's
+  CONSTANT c_mm_addr_enable   : NATURAL := 0;
+  CONSTANT c_cross_clock_domain_latency : NATURAL := 40;
+  
+  SIGNAL tb_end : STD_LOGIC := '0';
+  SIGNAL rst    : STD_LOGIC;
+  SIGNAL clk    : STD_LOGIC := '0';
+  
+  SIGNAL delay       : NATURAL   := 0;
+  SIGNAL trigger     : STD_LOGIC := '0';
+  SIGNAL trigger_dly : STD_LOGIC := '0';
+
+  SIGNAL mm_mosi     : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL mm_miso     : t_mem_miso;
+
+  SIGNAL enable      : NATURAL;
+BEGIN
+  clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+  rst <= '1', '0' AFTER c_clk_period*4;
+
+  p_mm_stimuli : PROCESS
+  BEGIN
+    WAIT UNTIL rst='0';
+    proc_common_wait_some_cycles(clk, 10);
+     
+    proc_mem_mm_bus_wr(c_mm_addr_enable, 1, clk, mm_miso, mm_mosi);
+    proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+    proc_mem_mm_bus_rd(c_mm_addr_enable, clk, mm_miso, mm_mosi);
+    proc_mem_mm_bus_rd_latency(1, clk);
+    enable <= TO_UINT(mm_miso.rddata(1 DOWNTO 0));
+    proc_common_wait_some_cycles(clk, 1);
+    ASSERT enable = 1 REPORT "enable not on" SEVERITY ERROR;
+
+    proc_mem_mm_bus_wr(c_mm_addr_enable, 0, clk, mm_miso, mm_mosi);
+    proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+    proc_mem_mm_bus_rd(c_mm_addr_enable, clk, mm_miso, mm_mosi);
+    proc_mem_mm_bus_rd_latency(1, clk);
+    enable <= TO_UINT(mm_miso.rddata(0 DOWNTO 0));
+    proc_common_wait_some_cycles(clk, 1);
+    ASSERT enable = 0 REPORT "enable not off" SEVERITY ERROR;
+
+    proc_common_wait_some_cycles(clk, 100);
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
+
+  -- generate trigger signal
+  proc_common_gen_pulse(c_trigger_interval/2, c_trigger_interval, '1', rst, clk, trigger);
+
+  -- device under test
+  u_dut : ENTITY work.mms_common_variable_delay
+  PORT MAP (
+    mm_rst     => rst,
+    mm_clk     => clk,
+    dp_rst     => rst,
+    dp_clk     => clk,
+
+    reg_enable_mosi => mm_mosi,
+    reg_enable_miso => mm_miso,
+
+    delay       => delay,
+    trigger     => trigger,
+    trigger_dly => trigger_dly
+  );
+      
+END tb;
+