Added g_default_value

libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd

@@ -38,6 +38,9 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 
 ENTITY dp_xonoff_reg IS
+  GENERIC ( 
+    g_default_value : STD_LOGIC := '1'
+  );
   PORT (
     -- Clocks and reset
     mm_rst            : IN  STD_LOGIC;
@@ -61,7 +64,7 @@ ARCHITECTURE str OF dp_xonoff_reg IS
                                   adr_w    => 1,
                                   dat_w    => c_word_w,
                                   nof_dat  => 1,
-                                  init_sl  => '0');
+                                  init_sl  => g_default_value);
 
   SIGNAL mm_xonoff_reg : STD_LOGIC_VECTOR(0 DOWNTO 0);
 
@@ -73,7 +76,7 @@ BEGIN
       -- Read access
       sla_out   <= c_mem_miso_rst;
       -- Write access, register values
-      mm_xonoff_reg(0) <= '1'; 
+      mm_xonoff_reg(0) <= g_default_value; 
    
     ELSIF rising_edge(mm_clk) THEN
       -- Read access defaults

libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd

@@ -30,7 +30,8 @@ ENTITY mms_dp_xonoff IS
   GENERIC (
     g_nof_streams     : NATURAL := 1;
     g_combine_streams : BOOLEAN := FALSE;
-    g_bypass          : BOOLEAN := FALSE
+    g_bypass          : BOOLEAN := FALSE;
+    g_default_value   : STD_LOGIC := '1'
   );
   PORT (
     -- Memory-mapped clock domain
@@ -82,6 +83,9 @@ BEGIN
 
   gen_reg : FOR i IN 0 TO c_nof_ctrl_streams-1 GENERATE
     u_reg : ENTITY work.dp_xonoff_reg
+    GENERIC MAP(
+      g_default_value => g_default_value
+    )
     PORT MAP (
       -- Clocks and reset
       mm_rst       => mm_rst,