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Commit 74c12d9c authored by Eric Kooistra's avatar Eric Kooistra
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Removed st_rst and xo_rst from unb2_board_node_ctrl. Improved structure to... 

Removed st_rst and xo_rst from unb2_board_node_ctrl. Improved structure to make the code more clear.
parent 8d9d8e14
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boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+ 108
− 64
View file @ 74c12d9c
......@@ -115,18 +115,22 @@ ENTITY ctrl_unb2_board IS
--
-- System
cs_sim : OUT STD_LOGIC;
xo_ethclk : OUT STD_LOGIC; -- 125 MHz ETH_CLK
xo_rst : OUT STD_LOGIC;
xo_rst_n : OUT STD_LOGIC;
mm_clk : OUT STD_LOGIC; -- from xo_ethclk PLL
ext_clk200 : OUT STD_LOGIC; -- 200 MHz CLK
ext_rst200 : OUT STD_LOGIC;
mm_clk : OUT STD_LOGIC; -- MM clock from xo_ethclk PLL
mm_rst : OUT STD_LOGIC;
dp_rst : OUT STD_LOGIC;
dp_clk : OUT STD_LOGIC; -- 200 MHz from CLK system clock
dp_clk : OUT STD_LOGIC; -- 200 MHz from CLK system clock direct or via PLL dependent on g_dp_clk_use_pll
dp_pps : OUT STD_LOGIC; -- PPS in dp_clk domain
dp_rst_in : IN STD_LOGIC; -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
dp_clk_in : IN STD_LOGIC; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk (due to dp_clk <= i_dp_clk assignment)
dp_clk_in : IN STD_LOGIC; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
this_chip_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0); -- [1:0], so range 0-3 for PN
this_bck_id : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
......@@ -221,10 +225,14 @@ END ctrl_unb2_board;
ARCHITECTURE str OF ctrl_unb2_board IS
CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
-- Clock and reset
SIGNAL i_ext_clk200 : STD_LOGIC;
SIGNAL ext_pps : STD_LOGIC;
SIGNAL i_xo_ethclk : STD_LOGIC;
SIGNAL i_xo_rst : STD_LOGIC;
SIGNAL i_xo_rst_n : STD_LOGIC;
SIGNAL i_mm_rst : STD_LOGIC;
SIGNAL i_mm_clk : STD_LOGIC;
SIGNAL mm_locked : STD_LOGIC;
......@@ -233,18 +241,11 @@ ARCHITECTURE str OF ctrl_unb2_board IS
SIGNAL clk125 : STD_LOGIC := '1';
SIGNAL clk100 : STD_LOGIC := '1';
SIGNAL clk50 : STD_LOGIC := '1';
SIGNAL i_dp_clk : STD_LOGIC := '1';
SIGNAL mm_wdi : STD_LOGIC;
SIGNAL eth1g_st_clk : STD_LOGIC;
SIGNAL eth1g_st_rst : STD_LOGIC;
SIGNAL ext_clk200 : STD_LOGIC;
SIGNAL ext_pps : STD_LOGIC;
SIGNAL node_ctrl_dp_clk_in : STD_LOGIC := '0';
SIGNAL node_ctrl_dp_rst_out : STD_LOGIC;
SIGNAL mm_pulse_ms : STD_LOGIC;
SIGNAL mm_pulse_s : STD_LOGIC;
SIGNAL mm_board_sens_start : STD_LOGIC;
......@@ -271,38 +272,77 @@ ARCHITECTURE str OF ctrl_unb2_board IS
BEGIN
ext_clk200 <= i_ext_clk200;
xo_ethclk <= i_xo_ethclk;
xo_rst <= i_xo_rst;
xo_rst_n <= i_xo_rst_n;
xo_rst_n <= NOT i_xo_rst;
mm_clk <= i_mm_clk;
mm_rst <= i_mm_rst;
-----------------------------------------------------------------------------
-- Node set up
-----------------------------------------------------------------------------
i_xo_rst <= NOT i_xo_rst_n;
-- Default leave unused INOUT tri-state
INTA <= 'Z';
INTB <= 'Z';
TESTIO <= (OTHERS=>'Z'); -- Leave unused INOUT tri-state
-- Clock and reset
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
ext_clk200 <= CLK; -- use the external 200 MHz CLK as ext_clk
ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
-----------------------------------------------------------------------------
-- ext_clk200 = CLK
-----------------------------------------------------------------------------
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : ENTITY common_lib.common_areset
GENERIC MAP (
g_rst_level => '1', -- power up default will be inferred in FPGA
g_delay_len => c_reset_len
)
PORT MAP (
in_rst => '0', -- release reset after some clock cycles
clk => i_ext_clk200,
out_rst => ext_rst200
);
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
-----------------------------------------------------------------------------
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : ENTITY common_lib.common_areset
GENERIC MAP (
g_rst_level => '1', -- power up default will be inferred in FPGA
g_delay_len => c_reset_len
)
PORT MAP (
in_rst => '0', -- release reset after some clock cycles
clk => i_xo_ethclk,
out_rst => i_xo_rst
);
gen_pll_dp_clk: IF g_dp_clk_use_pll = TRUE GENERATE
gen_pll_dp_clk_sim: IF g_sim = TRUE GENERATE
dp_clk <= i_dp_clk;
dp_rst <= '1', '0' AFTER 10 ns;
i_dp_clk <= NOT i_dp_clk AFTER 2.5 ns; -- 200MHz , 5ns/2
-----------------------------------------------------------------------------
-- dp_clk
-- . release dp_rst some clock cycles after mm_rst went low
-----------------------------------------------------------------------------
gen_dp_clk_sim: IF g_sim = TRUE GENERATE
dp_clk <= i_ext_clk200;
u_common_areset_st : ENTITY common_lib.common_areset
GENERIC MAP (
g_rst_level => '1',
g_delay_len => c_reset_len
)
PORT MAP (
in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
clk => dp_clk_in,
out_rst => dp_rst
);
END GENERATE;
gen_pll_dp_clk_pll: IF g_sim = FALSE GENERATE
gen_dp_clk_hardware: IF g_sim = FALSE GENERATE
gen_pll: IF g_dp_clk_use_pll = TRUE GENERATE
u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
GENERIC MAP (
g_technology => g_technology,
......@@ -310,18 +350,34 @@ BEGIN
)
PORT MAP (
arst => i_mm_rst,
clk200 => ext_clk200,
clk200 => i_ext_clk200,
st_clk200 => dp_clk, -- = c0
st_rst200 => dp_rst
);
END GENERATE;
END GENERATE;
no_pll_dp_clk: IF g_dp_clk_use_pll = FALSE GENERATE
dp_rst <= node_ctrl_dp_rst_out;
node_ctrl_dp_clk_in <= dp_clk_in;
no_pll: IF g_dp_clk_use_pll = FALSE GENERATE
dp_clk <= i_ext_clk200;
u_common_areset_st : ENTITY common_lib.common_areset
GENERIC MAP (
g_rst_level => '1',
g_delay_len => c_reset_len
)
PORT MAP (
in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
clk => dp_clk_in,
out_rst => dp_rst
);
END GENERATE;
END GENERATE;
-----------------------------------------------------------------------------
-- mm_clk
-- . use mm_sim_clk in sim
-- . derived from ETH_CLK via PLL on hardware
-----------------------------------------------------------------------------
i_mm_clk <= mm_sim_clk WHEN g_sim = TRUE ELSE
clk125 WHEN g_mm_clk_freq = c_unb2_board_mm_clk_freq_125M ELSE
......@@ -329,25 +385,22 @@ BEGIN
clk50 WHEN g_mm_clk_freq = c_unb2_board_mm_clk_freq_50M ELSE
clk50; -- default
gen_pll_mm_clk_sim: IF g_sim = TRUE GENERATE
mm_locked <= '0', '1' AFTER 70 ns;
mm_sim_clk <= NOT mm_sim_clk AFTER 50 ns; -- 10 MHz, 100ns/2
gen_mm_clk_sim: IF g_sim = TRUE GENERATE
epcs_clk <= NOT epcs_clk AFTER 25 ns; -- 20 MHz, 50ns/2
clk50 <= NOT clk50 AFTER 10 ns; -- 50 MHz, 20ns/2
clk100 <= NOT clk100 AFTER 5 ns; -- 100 MHz, 10ns/2
clk125 <= NOT clk125 AFTER 4 ns; -- 125 MHz, 8ns/2
mm_sim_clk <= NOT mm_sim_clk AFTER 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
mm_locked <= '0', '1' AFTER 70 ns;
END GENERATE;
gen_pll_mm_clk_pll: IF g_sim = FALSE GENERATE
--u_unb2_board_clk200mm_pll : ENTITY work.unb2_board_clk200mm_pll
gen_mm_clk_hardware: IF g_sim = FALSE GENERATE
u_unb2_board_clk125_pll : ENTITY work.unb2_board_clk125_pll
GENERIC MAP (
g_technology => g_technology
)
PORT MAP (
arst => i_xo_rst,
--clk200mm => ext_clk200,
clk125 => i_xo_ethclk,
c0_clk20 => epcs_clk,
c1_clk50 => clk50,
......@@ -357,34 +410,28 @@ BEGIN
);
END GENERATE;
u_unb2_board_node_ctrl : ENTITY work.unb2_board_node_ctrl
GENERIC MAP (
g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
PORT MAP (
-- xo_clk domain
xo_clk => i_xo_ethclk,
xo_rst_n => i_xo_rst_n,
-- mm_clk domain
-- MM clock domain reset
mm_clk => i_mm_clk,
mm_locked => mm_locked,
mm_rst => i_mm_rst,
-- WDI extend
mm_wdi_in => pout_wdi,
mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
-- Pulses
mm_pulse_us => OPEN,
mm_pulse_ms => mm_pulse_ms,
mm_pulse_s => mm_pulse_s, -- could be used to toggle a LED
-- st_clk domain
st_clk => node_ctrl_dp_clk_in,
st_rst => node_ctrl_dp_rst_out
mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
-----------------------------------------------------------------------------
-- System info
-----------------------------------------------------------------------------
cs_sim <= is_true(g_sim);
u_mms_unb2_board_system_info : ENTITY work.mms_unb2_board_system_info
......@@ -583,9 +630,6 @@ BEGIN
);
------------------------------------------------------------------------------
-- Ethernet 1GbE
------------------------------------------------------------------------------
......@@ -623,8 +667,8 @@ BEGIN
END GENERATE;
gen_mac: IF g_sim = FALSE GENERATE
u_mac : ENTITY eth_lib.eth
gen_eth: IF g_sim = FALSE GENERATE
u_eth : ENTITY eth_lib.eth
GENERIC MAP (
g_technology => g_technology,
g_cross_clock_domain => g_udp_offload
......
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