- Made chenged to fit in RadioHDL

applications/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd

@@ -25,15 +25,16 @@
 --          that are used on hardware. 
 
 
-LIBRARY IEEE, common_lib, unb_common_lib, i2c_lib, bf_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, bf_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
-USE unb_common_lib.unb_common_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
 USE bf_lib.bf_pkg.ALL;
 
-ENTITY tb_fn_bf IS
+ENTITY tb_unb1_fn_bf IS
 GENERIC(
   --   TYPE t_c_bf IS RECORD
   --    nof_signal_paths  : POSITIVE; -- = 64
@@ -52,18 +53,18 @@ GENERIC(
   --  END RECORD;
   g_bf : t_c_bf := (64, 16, 24, 256, 4, 16, 16, 1, 16, -5, 8, 56, 2)
 );
-END tb_fn_bf;
+END tb_unb1_fn_bf;
 
-ARCHITECTURE tb OF tb_fn_bf IS
+ARCHITECTURE tb OF tb_unb1_fn_bf IS
 
   CONSTANT c_sim             : BOOLEAN := TRUE;
 
   CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
   CONSTANT c_node_nr         : NATURAL := 3; -- Front node 3
-  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb_nof_chip_w);
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w ) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
 
   CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
-  CONSTANT c_fw_version      : t_unb_fw_version := (1, 0);
+  CONSTANT c_fw_version      : t_unb1_board_fw_version := (1, 0);
 
   CONSTANT c_cable_delay     : TIME := 12 ns;
   CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
@@ -83,9 +84,9 @@ ARCHITECTURE tb OF tb_fn_bf IS
   SIGNAL eth_txp             : STD_LOGIC;
   SIGNAL eth_rxp             : STD_LOGIC;
   
-  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb_aux.version_w-1 DOWNTO 0) := c_version; 
-  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb_aux.id_w-1 DOWNTO 0)      := c_id;
-  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb_aux.testio_w-1 DOWNTO 0);
+  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version; 
+  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)      := c_id;
+  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
 
   SIGNAL sens_scl            : STD_LOGIC;
   SIGNAL sens_sda            : STD_LOGIC;
@@ -129,7 +130,7 @@ BEGIN
   ------------------------------------------------------------------------------
   -- DUT
   ------------------------------------------------------------------------------
-  u_dut : ENTITY work.fn_bf
+  u_dut : ENTITY work.unb1_fn_bf
     GENERIC MAP (
       g_sim         => c_sim,
       g_sim_unb_nr  => c_unb_nr,
@@ -157,43 +158,5 @@ BEGIN
       ETH_SGIN    => eth_rxp,
       ETH_SGOUT   => eth_txp
     );
-    
-  ------------------------------------------------------------------------------
-  -- UniBoard sensors
-  ------------------------------------------------------------------------------
-  -- I2C slaves that are available for each FPGA
-  u_fpga_temp : ENTITY i2c_lib.dev_max1618
-  GENERIC MAP (
-    g_address => c_fpga_temp_address
-  )
-  PORT MAP (
-    scl  => sens_scl,
-    sda  => sens_sda,
-    temp => c_fpga_temp
-  );
-
-  -- I2C slaves that are available only via FPGA back node 3
-  u_eth_temp : ENTITY i2c_lib.dev_max1618
-  GENERIC MAP (
-    g_address => c_eth_temp_address
-  )
-  PORT MAP (
-    scl  => sens_scl,
-    sda  => sens_sda,
-    temp => c_eth_temp
-  );
   
-  u_power : ENTITY i2c_lib.dev_ltc4260
-  GENERIC MAP (
-    g_address => c_hot_swap_address,
-    g_R_sense => c_hot_swap_R_sense
-  )
-  PORT MAP (
-    scl               => sens_scl,
-    sda               => sens_sda,
-    ana_current_sense => c_uniboard_current,
-    ana_volt_source   => c_uniboard_supply,
-    ana_volt_adin     => c_uniboard_adin
-  );
-
 END tb;