Skip to content
Snippets Groups Projects
Commit 73d815ce authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Merge branch 'master' into L2SDP-210

parents 55d7fd22 87cdfe9f
No related branches found
No related tags found
1 merge request!190Resolve L2SDP-210
Pipeline #23633 passed
Stage: simulation
Stage: synthesis
Hide whitespace changes
Inline Side-by-side
libraries/dsp/st/src/vhdl/st_histogram.vhd
+ 6
− 8
View file @ 73d815ce
...@@ -137,10 +137,10 @@ ARCHITECTURE rtl OF st_histogram IS ...@@ -137,10 +137,10 @@ ARCHITECTURE rtl OF st_histogram IS
-- snk_in_reg_arr -- snk_in_reg_arr
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
CONSTANT c_ram_rd_wr_latency : NATURAL := 3; -- RAM read,incr,write cycle latency CONSTANT c_ram_rd_wr_latency : NATURAL := 3; -- RAM read,incr,write cycle latency
CONSTANT c_shiftreg_depth : NATURAL := c_ram_rd_wr_latency; CONSTANT c_shiftreg_depth : NATURAL := c_ram_rd_wr_latency+1;
SIGNAL snk_in_reg_arr : t_dp_sosi_arr(c_shiftreg_depth DOWNTO 0); SIGNAL snk_in_reg_arr : t_dp_sosi_arr(c_shiftreg_depth-1 DOWNTO 0);
SIGNAL nxt_snk_in_reg_arr : t_dp_sosi_arr(c_shiftreg_depth DOWNTO 0); SIGNAL nxt_snk_in_reg_arr : t_dp_sosi_arr(c_shiftreg_depth-1 DOWNTO 0);
SIGNAL snk_in_reg : t_dp_sosi; SIGNAL snk_in_reg : t_dp_sosi;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -250,11 +250,9 @@ BEGIN ...@@ -250,11 +250,9 @@ BEGIN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
p_nxt_snk_in_reg_arr: PROCESS(snk_in, snk_in_data, snk_in_reg_arr) IS p_nxt_snk_in_reg_arr: PROCESS(snk_in, snk_in_data, snk_in_reg_arr) IS
BEGIN BEGIN
nxt_snk_in_reg_arr <= snk_in_reg_arr; FOR i IN 0 TO c_shiftreg_depth-1 LOOP
nxt_snk_in_reg_arr(3).valid <= '0'; nxt_snk_in_reg_arr(i) <= c_dp_sosi_rst;
--FOR i IN 0 TO c_shiftreg_depth-1 LOOP END LOOP;
-- nxt_snk_in_reg_arr(i) <= c_dp_sosi_rst;
--END LOOP;
IF snk_in.valid='1' THEN IF snk_in.valid='1' THEN
-- The base function is a shift register -- The base function is a shift register
......
libraries/dsp/verify_pfb/hdllib.cfg
+ 2
− 2
View file @ 73d815ce
...@@ -25,8 +25,8 @@ modelsim_copy_files = ...@@ -25,8 +25,8 @@ modelsim_copy_files =
../filter/src/hex data # PFIR filter coefficients ../filter/src/hex data # PFIR filter coefficients
../wpfb/tb/data data ../wpfb/tb/data data
# LOFAR1 pfs + pft2 # LOFAR1 pfs + pft2
$RADIOHDL_WORK/applications/lofar1/pfs/src/data data # FIR filter coefficients $RADIOHDL_WORK/applications/lofar1/RSP/pfs/src/data data # FIR filter coefficients
$RADIOHDL_WORK/applications/lofar1/pft2/src/data data # FFT twiddle factors $RADIOHDL_WORK/applications/lofar1/RSP/pft2/src/data data # FFT twiddle factors
[quartus_project_file] [quartus_project_file]
libraries/dsp/wpfb/hdllib.cfg
+ 2
− 2
View file @ 73d815ce
...@@ -29,8 +29,8 @@ modelsim_copy_files = ...@@ -29,8 +29,8 @@ modelsim_copy_files =
tb/data data tb/data data
../../base/diag/src/data data # WG ../../base/diag/src/data data # WG
# LOFAR1 pfs + pft2 # LOFAR1 pfs + pft2
$RADIOHDL_WORK/applications/lofar1/pfs/src/data data # FIR filter coefficients $RADIOHDL_WORK/applications/lofar1/RSP/pfs/src/data data # FIR filter coefficients
$RADIOHDL_WORK/applications/lofar1/pft2/src/data data # Twiddle factors $RADIOHDL_WORK/applications/lofar1/RSP/pft2/src/data data # Twiddle factors
[quartus_project_file] [quartus_project_file]
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment