Added mm_latency_adapter.vhd to prepare for supporting pipeline of miso.waitrequest.

libraries/base/mm/hdllib.cfg

@@ -13,6 +13,7 @@ synth_files =
     src/verilog/wbs_arbiter.v
     src/vhdl/mm_arbiter.vhd
     
+    src/vhdl/mm_latency_adapter.vhd
     src/vhdl/mm_bus.vhd
     src/vhdl/mm_master_mux.vhd
     src/vhdl/mm_slave_mux.vhd

libraries/base/mm/src/vhdl/mm_latency_adapter.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- 
+-- Author: E. Kooistra
+-- Purpose: Adapt miso.waitrequest latency from 1 to 0, to support pipelining
+--          of the waitrequest flow control
+-- Description:
+--   Wraps common_rl_decrease.vhd.
+--   The common_rl_decrease.vhd latency adapter FIFO buffers the in_mosi, to
+--   create time to compensate for the pipeline of the in_mosi.waitrequest.
+--   When the in_mosi.waitrequest goes high, then this FIFO buffer can hold
+--   the in_mosi input that may still arrive, due to that the master at the
+--   input only notices the in_mosi.waitrequest from the output slave one
+--   cylce later due to the pipelining.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_latency_adapter IS
+  GENERIC (
+    g_adapt       : BOOLEAN := TRUE    -- default when TRUE then decrease sink RL 1 to source RL 0, else then implement wires
+  );
+  PORT (
+    mm_rst        : IN  STD_LOGIC;
+    mm_clk        : IN  STD_LOGIC;
+    -- MM input RL = 1
+    in_mosi       : IN  t_mem_mosi;
+    in_miso       : OUT t_mem_miso;
+    -- MM output RL = 0
+    out_mosi      : OUT t_mem_mosi;
+    out_miso      : IN  t_mem_miso
+  );
+END mm_latency_adapter;
+
+
+ARCHITECTURE str OF mm_latency_adapter IS
+
+  -- Sum of all t_mem_mosi fields widths: 32 + 72 + 1 (wr) + 1 (rd)
+  CONSTANT c_data_w  : NATURAL := c_mem_address_w +  c_mem_data_w + 2;
+
+  SIGNAL in_data         : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+  SIGNAL in_val          : STD_LOGIC;
+  SIGNAL in_waitrequest  : STD_LOGIC;
+  SIGNAL out_data        : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+  SIGNAL out_val         : STD_LOGIC;
+    
+BEGIN
+
+  in_data <= func_slv_concat(in_mosi.address, in_mosi.wrdata, slv(in_mosi.wr), slv(in_mosi.rd));
+  in_val <= in_mosi.wr OR in_mosi.rd;
+
+  p_miso : PROCESS(out_miso, in_waitrequest)
+  BEGIN       
+    in_miso <= out_miso;
+    in_miso.waitrequest <= in_waitrequest;
+  END PROCESS;
+
+  u_rl : ENTITY common_lib.common_rl_decrease
+  GENERIC MAP (
+    g_adapt   => g_adapt,
+    g_dat_w   => c_data_w
+  )
+  PORT MAP (
+    rst           => mm_rst,
+    clk           => mm_clk,
+    -- ST sink: RL = 1
+    snk_out_ready => in_waitrequest,
+    snk_in_dat    => in_data,
+    snk_in_val    => in_val,
+    -- ST source: RL = 0
+    src_in_ready  => out_miso.waitrequest,
+    src_out_dat   => out_data,
+    src_out_val   => out_val
+  );
+  
+  out_mosi.address <=    func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 0);
+  out_mosi.wrdata  <=    func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 1);
+  out_mosi.wr      <= sl(func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 2));
+  out_mosi.rd      <= sl(func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 3));
+  
+END str;