Demo myHDL 25 sep 2014 by Daniel van der Schuur.

tools/oneclick/prestudy/oneclick_prestudy_readme.txt

@@ -125,8 +125,32 @@ This file keeps some historical notes on the OneClick prestudy results.
      but can higher level ports like DP and MM build on that to avoid showing
      all the DP and MM port details in the model?
      
+6) Demo myHDL 25 sep 2014 by Daniel van der Schuur
 
-6) Action points
+   $SVN/RadioHDL/trunk/tools/oneclick/prestudy/myHDL/
+   
+   python tb_block_gen.py       --> RTL simulation, Wave view with gtk_wave.
+   python muxed_block_gens.py   --> RTL toVHDL() code generation
+   
+  The myHDL could be a layer in our OneClick environment:
+  
+     4 our Model (using lists, no clock, running on processes)
+     3 myHDL
+     2 our VHDL components, myHDL RTL
+     1 complete design in VHDL
+  
+  MyHDL can offer functionality that we also need:
+  
+  - hierarchy
+  - connecting components
+  - generics (in Python input/output port and generics are all method arguments,
+      the constant arguments become named constants in the generated VHDL)
+ 
+  For SA the myHDL could be the entry level. On top of myHDL for use the 
+  model could be the entry level.
+  
+  
+7) Action points
 
   It is to early to actually start implemeting e.g. parts of the code
   generation like parsing a VHDL entity, first we need to:
@@ -134,6 +158,8 @@ This file keeps some historical notes on the OneClick prestudy results.
   a Get more clear what is needed for a python base class for modelling and
     code generation.
   b Think of more use cases to find out what we need to represent and how.
+  c Can we make good use of myHDL while still being able to model lists,
+    so without clock.
 
   DS  . 
   HJP Review the demo code and update the Oneclick document SP-056