Add a small FIFO to suppress word loss in next eth_hdr module during ihl correction

libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd

@@ -80,6 +80,7 @@ END eth_ihl_to_20;
 ARCHITECTURE rtl OF eth_ihl_to_20 IS
 
   SIGNAL i_src_out        : t_dp_sosi;
+  SIGNAL i_src_in         : t_dp_siso;
   
   TYPE state_type IS (Idle, Eth_DestMAC0, Eth_DestMAC1, Eth_SrcMAC0, Eth_SrcMAC1, IPv4_lengths, IPv4_ID, IPv4_TTL, IPv4_SrcIP, IPv4_DestIP, IPv4_Options, IPv4_Payload);
   SIGNAL state   : state_type;
@@ -88,14 +89,31 @@ ARCHITECTURE rtl OF eth_ihl_to_20 IS
   
 BEGIN
 
-  src_out <= i_src_out;
-  --i_src_out <= snk_in;
 
   -- Pass on frame level flow control
-  snk_out.xon <= src_in.xon;
+  snk_out.xon <= i_src_in.xon;
   
   -- No change in ready latency, c_this_snk_latency = c_this_src_latency
-  snk_out.ready <= src_in.ready;
+  snk_out.ready <= i_src_in.ready;
+
+  u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+  GENERIC MAP (
+    g_data_w    => c_eth_data_w,
+    g_use_bsn   => FALSE,
+    g_use_sync  => FALSE,
+    g_fifo_size => 10 
+   )
+  PORT MAP (
+    rst        => rst,
+    clk        => clk,
+  
+    snk_in     => i_src_out,
+    snk_out    => i_src_in,
+  
+    src_out    => src_out,
+    src_in     => src_in
+  );
+
   
 
   PROCESS(clk, rst)