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Commit 6efda252 authored by Eric Kooistra's avatar Eric Kooistra
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Updated the description to highlight the limitations.

parent 7685c482
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2 merge requests!28Master,!15Resolve L2SDP-27
......@@ -66,14 +66,6 @@
-- v
-- master_miso <--------------------slave_miso_arr[ ]<-- slave_miso_arr
--
-- A limitation is that if one slave has a read latency of 2 and another
-- slave has a read latency of 1 then it is not possible to access them
-- without a gap of 1 mm_clk cycle, because the rdval will then be active
-- simultaneously from both slaves. Therefore the master can only use
-- random read access between slaves if all slaves have the same read
-- latency. For slaves that have larger read latency the master must
-- insert an gap, before it can read a slave that has less read latency.
--
-- * Pipelining
-- Default the common_mm_bus is combinatorial, so there is no pipelining
-- between the master interface and the slave interfaces. If possible do not
......@@ -98,6 +90,20 @@
-- c_pipeline_mosi + g_rd_latency_arr of the selected slave +
-- c_pipeline_miso_rd.
--
-- Limitations:
-- * A limitation is that if one slave has a read latency of 2 and another
-- slave has a read latency of 1 then it is not possible to access them
-- without a gap of 1 mm_clk cycle, because the rdval will then be active
-- simultaneously from both slaves. Therefore the master can only use
-- random read access between slaves if all slaves have the same read
-- latency. For slaves that have larger read latency the master must
-- insert an gap, before it can read a slave that has less read latency.
-- An alternative workaround would be to use the same read latency for all
-- slaves on the bus, by pipelining the miso.rd, rddata for MM slaves that
-- have a smaller read latency.
-- * No support yet for g_pipeline_miso_wait = TRUE. This requires an MM
-- latency adapter for the mosi dependent on the miso.waitrequest.
--
-- Remarks:
-- . The common_mem_bus resembles common_mem_mux, but the difference is that
-- with common_mem_mux all slaves have the same address range and are
......
......@@ -39,8 +39,16 @@
-- extra latency. The mm_clk is needed to hold the index of the master that
-- is currently active, to ensure that the read data.is passed on to the
-- master that did the rd access.
--
-- Remarks:
-- . The mux_miso.waitrequest is not supported.
-- . There is no bus arbitrator. This is sufficient for use cases where e.g.
-- one master only does some initialization accesses after reset and the
-- other master is the main master that does all subsequent accesses.
-- Therefore this common_mem_master_mux is typically suited per MM slave
-- that needs dual master access, rather then to select between two main
-- central MM masters.
-- . There is no pipelining. The advantage is that the mux_miso.waitrequest is
-- supported without extra effort.
--
-------------------------------------------------------------------------------
......
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