initila

boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg

+hdl_lib_name = unb1_fn_terminal_db
+hdl_library_clause_name = unb1_fn_terminal_db_lib
+hdl_lib_uses_synth = common technology mm i2c unb1_board diag 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_top_level_entity =
+
+synth_files =   
+    $HDL_BUILD_DIR/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
+    src/vhdl/mmm_unb1_fn_terminal_db.vhd
+    src/vhdl/node_unb1_fn_terminal_db.vhd
+    src/vhdl/unb1_fn_terminal_db.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_unb1_fn_terminal_db.vhd
+
+#modelsim_copy_files = src/hex hex                                                   
+
+quartus_copy_files = quartus/sopc_unb1_fn_terminal_db.sopc .
+
+quartus_qsf_files =                                                       
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+    quartus/unb1_fn_terminal_db_pins.tcl
+    
+quartus_qip_files =
+    $HDL_BUILD_DIR/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
+