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RTSD
HDL
Commits
6e612423
Commit
6e612423
authored
3 years ago
by
Eric Kooistra
Browse files
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Added verification for w =4, r = 2, 3 amd for w = 5, r = 3.
parent
ad09a2e9
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1 merge request
!168
Add support for round half to even via g_round_even. Not yet fully tested....
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2
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libraries/base/common/tb/vhdl/tb_round.vhd
+231
-57
231 additions, 57 deletions
libraries/base/common/tb/vhdl/tb_round.vhd
libraries/base/common/tb/vhdl/tb_tb_round.vhd
+3
-0
3 additions, 0 deletions
libraries/base/common/tb/vhdl/tb_tb_round.vhd
with
234 additions
and
57 deletions
libraries/base/common/tb/vhdl/tb_round.vhd
+
231
−
57
View file @
6e612423
...
...
@@ -24,7 +24,9 @@
-- Description:
-- The signal names in this VHDL tb are the same as in the document [1] and
-- in the Python tb [2].
-- The verification uses expected results from [2].
-- The verification uses expected results that were obtained and copied
-- from [2]. The tb_tb_round.vhd tries different settings for w and r.
--
-- References:
-- [1] https://support.astron.nl/confluence/display/L2M/L4+SDPFW+Decision%3A+Number+representation%2C+resizing+and+rounding
-- [2] common_round_tb.py
...
...
@@ -40,8 +42,8 @@ USE work.common_pkg.ALL;
ENTITY
tb_round
IS
GENERIC
(
g_in_dat_w
:
NATURAL
:
=
4
;
g_out_dat_w
:
NATURAL
:
=
3
g_in_dat_w
:
NATURAL
:
=
4
;
-- w = g_in_dat_w, in [2]
g_out_dat_w
:
NATURAL
:
=
1
-- r = g_in_dat_w - g_out_dat_w, in [2]
);
END
tb_round
;
...
...
@@ -56,32 +58,79 @@ ARCHITECTURE tb OF tb_round IS
CONSTANT
c_round_w
:
INTEGER
:
=
g_in_dat_w
-
g_out_dat_w
;
-- Expected rounded results from [2] for w = g_in_dat_w = 4 and r = c_round_w = 1
CONSTANT
c_exp_w4_r1_signed_truncate
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-3
,
-2
,
-2
,
-1
,
-1
,
0
,
0
,
1
,
1
,
2
,
2
,
3
,
3
);
CONSTANT
c_exp_w4_r1_signed_round_half_away
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-3
,
-2
,
-2
,
-1
,
-1
,
0
,
1
,
1
,
2
,
2
,
3
,
3
,
-4
);
CONSTANT
c_exp_w4_r1_signed_round_half_away_clip
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-3
,
-2
,
-2
,
-1
,
-1
,
0
,
1
,
1
,
2
,
2
,
3
,
3
,
3
);
CONSTANT
c_exp_w4_r1_signed_round_half_even
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-2
,
-2
,
-2
,
-1
,
0
,
0
,
0
,
1
,
2
,
2
,
2
,
3
,
-4
);
CONSTANT
c_exp_w4_r1_signed_round_half_even_clip
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-2
,
-2
,
-2
,
-1
,
0
,
0
,
0
,
1
,
2
,
2
,
2
,
3
,
3
);
CONSTANT
c_exp_w4_r1_unsigned_truncate
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
1
,
1
,
2
,
2
,
3
,
3
,
4
,
4
,
5
,
5
,
6
,
6
,
7
,
7
);
CONSTANT
c_exp_w4_r1_unsigned_round_half_up
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
1
,
1
,
2
,
2
,
3
,
3
,
4
,
4
,
5
,
5
,
6
,
6
,
7
,
7
,
0
);
CONSTANT
c_exp_w4_r1_unsigned_round_half_up_clip
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
1
,
1
,
2
,
2
,
3
,
3
,
4
,
4
,
5
,
5
,
6
,
6
,
7
,
7
,
7
);
CONSTANT
c_exp_w4_r1_unsigned_round_half_even
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
1
,
2
,
2
,
2
,
3
,
4
,
4
,
4
,
5
,
6
,
6
,
6
,
7
,
0
);
CONSTANT
c_exp_w4_r1_unsigned_round_half_even_clip
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
1
,
2
,
2
,
2
,
3
,
4
,
4
,
4
,
5
,
6
,
6
,
6
,
7
,
7
);
CONSTANT
c_exp_w4_r1_sreal_fixed_point
:
t_real_arr
(
0
TO
15
)
:
=
(
-4
.
0
,
-3
.
5
,
-3
.
0
,
-2
.
5
,
-2
.
0
,
-1
.
5
,
-1
.
0
,
-0
.
5
,
0
.
0
,
0
.
5
,
1
.
0
,
1
.
5
,
2
.
0
,
2
.
5
,
3
.
0
,
3
.
5
);
CONSTANT
c_exp_w4_r1_signed_truncate
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-3
,
-2
,
-2
,
-1
,
-1
,
0
,
0
,
1
,
1
,
2
,
2
,
3
,
3
);
CONSTANT
c_exp_w4_r1_signed_round_half_away
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-3
,
-2
,
-2
,
-1
,
-1
,
0
,
1
,
1
,
2
,
2
,
3
,
3
,
-4
);
CONSTANT
c_exp_w4_r1_signed_round_half_away_clip
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-3
,
-2
,
-2
,
-1
,
-1
,
0
,
1
,
1
,
2
,
2
,
3
,
3
,
3
);
CONSTANT
c_exp_w4_r1_signed_round_half_even
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-2
,
-2
,
-2
,
-1
,
0
,
0
,
0
,
1
,
2
,
2
,
2
,
3
,
-4
);
CONSTANT
c_exp_w4_r1_signed_round_half_even_clip
:
t_integer_arr
(
0
TO
15
)
:
=
(
-4
,
-4
,
-3
,
-2
,
-2
,
-2
,
-1
,
0
,
0
,
0
,
1
,
2
,
2
,
2
,
3
,
3
);
CONSTANT
c_exp_w4_r1_unsigned_fixed_point
:
t_real_arr
(
0
TO
15
)
:
=
(
0
.
0
,
0
.
5
,
1
.
0
,
1
.
5
,
2
.
0
,
2
.
5
,
3
.
0
,
3
.
5
,
4
.
0
,
4
.
5
,
5
.
0
,
5
.
5
,
6
.
0
,
6
.
5
,
7
.
0
,
7
.
5
);
CONSTANT
c_exp_w4_r1_unsigned_truncate
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
1
,
1
,
2
,
2
,
3
,
3
,
4
,
4
,
5
,
5
,
6
,
6
,
7
,
7
);
CONSTANT
c_exp_w4_r1_unsigned_round_half_up
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
1
,
1
,
2
,
2
,
3
,
3
,
4
,
4
,
5
,
5
,
6
,
6
,
7
,
7
,
0
);
CONSTANT
c_exp_w4_r1_unsigned_round_half_up_clip
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
1
,
1
,
2
,
2
,
3
,
3
,
4
,
4
,
5
,
5
,
6
,
6
,
7
,
7
,
7
);
CONSTANT
c_exp_w4_r1_unsigned_round_half_even
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
1
,
2
,
2
,
2
,
3
,
4
,
4
,
4
,
5
,
6
,
6
,
6
,
7
,
0
);
CONSTANT
c_exp_w4_r1_unsigned_round_half_even_clip
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
1
,
2
,
2
,
2
,
3
,
4
,
4
,
4
,
5
,
6
,
6
,
6
,
7
,
7
);
-- Expected rounded results from [2] for w = g_in_dat_w = 4 and r = c_round_w = 2
CONSTANT
c_exp_w4_r2_sreal_fixed_point
:
t_real_arr
(
0
TO
15
)
:
=
(
-2
.
0
,
-1
.
75
,
-1
.
5
,
-1
.
25
,
-1
.
0
,
-0
.
75
,
-0
.
5
,
-0
.
25
,
0
.
0
,
0
.
25
,
0
.
5
,
0
.
75
,
1
.
0
,
1
.
25
,
1
.
5
,
1
.
75
);
CONSTANT
c_exp_w4_r2_signed_truncate
:
t_integer_arr
(
0
TO
15
)
:
=
(
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
);
CONSTANT
c_exp_w4_r2_signed_round_half_away
:
t_integer_arr
(
0
TO
15
)
:
=
(
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
-2
,
-2
);
CONSTANT
c_exp_w4_r2_signed_round_half_away_clip
:
t_integer_arr
(
0
TO
15
)
:
=
(
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
);
CONSTANT
c_exp_w4_r2_signed_round_half_even
:
t_integer_arr
(
0
TO
15
)
:
=
(
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
-2
,
-2
);
CONSTANT
c_exp_w4_r2_signed_round_half_even_clip
:
t_integer_arr
(
0
TO
15
)
:
=
(
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
);
CONSTANT
c_exp_w4_r2_unsigned_fixed_point
:
t_real_arr
(
0
TO
15
)
:
=
(
0
.
0
,
0
.
25
,
0
.
5
,
0
.
75
,
1
.
0
,
1
.
25
,
1
.
5
,
1
.
75
,
2
.
0
,
2
.
25
,
2
.
5
,
2
.
75
,
3
.
0
,
3
.
25
,
3
.
5
,
3
.
75
);
CONSTANT
c_exp_w4_r2_unsigned_truncate
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w4_r2_unsigned_round_half_up
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
0
,
0
);
CONSTANT
c_exp_w4_r2_unsigned_round_half_up_clip
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w4_r2_unsigned_round_half_even
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
0
,
0
);
CONSTANT
c_exp_w4_r2_unsigned_round_half_even_clip
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
);
-- Expected rounded results from [2] for w = g_in_dat_w = 4 and r = c_round_w = 3
CONSTANT
c_exp_w4_r3_sreal_fixed_point
:
t_real_arr
(
0
TO
15
)
:
=
(
-1
.
0
,
-0
.
875
,
-0
.
75
,
-0
.
625
,
-0
.
5
,
-0
.
375
,
-0
.
25
,
-0
.
125
,
0
.
0
,
0
.
125
,
0
.
25
,
0
.
375
,
0
.
5
,
0
.
625
,
0
.
75
,
0
.
875
);
CONSTANT
c_exp_w4_r3_signed_truncate
:
t_integer_arr
(
0
TO
15
)
:
=
(
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
);
CONSTANT
c_exp_w4_r3_signed_round_half_away
:
t_integer_arr
(
0
TO
15
)
:
=
(
-1
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
-1
,
-1
,
-1
,
-1
);
CONSTANT
c_exp_w4_r3_signed_round_half_away_clip
:
t_integer_arr
(
0
TO
15
)
:
=
(
-1
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
);
CONSTANT
c_exp_w4_r3_signed_round_half_even
:
t_integer_arr
(
0
TO
15
)
:
=
(
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
-1
,
-1
,
-1
);
CONSTANT
c_exp_w4_r3_signed_round_half_even_clip
:
t_integer_arr
(
0
TO
15
)
:
=
(
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
);
CONSTANT
c_exp_w4_r3_unsigned_fixed_point
:
t_real_arr
(
0
TO
15
)
:
=
(
0
.
0
,
0
.
125
,
0
.
25
,
0
.
375
,
0
.
5
,
0
.
625
,
0
.
75
,
0
.
875
,
1
.
0
,
1
.
125
,
1
.
25
,
1
.
375
,
1
.
5
,
1
.
625
,
1
.
75
,
1
.
875
);
CONSTANT
c_exp_w4_r3_unsigned_truncate
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
);
CONSTANT
c_exp_w4_r3_unsigned_round_half_up
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
0
,
0
,
0
,
0
);
CONSTANT
c_exp_w4_r3_unsigned_round_half_up_clip
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
);
CONSTANT
c_exp_w4_r3_unsigned_round_half_even
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
0
,
0
,
0
,
0
);
CONSTANT
c_exp_w4_r3_unsigned_round_half_even_clip
:
t_natural_arr
(
0
TO
15
)
:
=
(
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
);
-- Expected rounded results from [2] for w = g_in_dat_w = 5 and r = c_round_w = 2
CONSTANT
c_exp_w5_r2_signed_truncate
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w5_r2_signed_round_half_away
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
-4
,
-4
);
CONSTANT
c_exp_w5_r2_signed_round_half_away_clip
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w5_r2_signed_round_half_even
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
-4
,
-4
);
CONSTANT
c_exp_w5_r2_signed_round_half_even_clip
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w5_r2_unsigned_truncate
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
);
CONSTANT
c_exp_w5_r2_unsigned_truncate_symmetric
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
);
CONSTANT
c_exp_w5_r2_unsigned_round_half_up
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
,
0
,
0
);
CONSTANT
c_exp_w5_r2_unsigned_round_half_up_clip
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
,
7
,
7
);
CONSTANT
c_exp_w5_r2_unsigned_round_half_even
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
0
,
0
);
CONSTANT
c_exp_w5_r2_unsigned_round_half_even_clip
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
,
7
);
CONSTANT
c_exp_w5_r2_sreal_fixed_point
:
t_real_arr
(
0
TO
31
)
:
=
(
-4
.
0
,
-3
.
75
,
-3
.
5
,
-3
.
25
,
-3
.
0
,
-2
.
75
,
-2
.
5
,
-2
.
25
,
-2
.
0
,
-1
.
75
,
-1
.
5
,
-1
.
25
,
-1
.
0
,
-0
.
75
,
-0
.
5
,
-0
.
25
,
0
.
0
,
0
.
25
,
0
.
5
,
0
.
75
,
1
.
0
,
1
.
25
,
1
.
5
,
1
.
75
,
2
.
0
,
2
.
25
,
2
.
5
,
2
.
75
,
3
.
0
,
3
.
25
,
3
.
5
,
3
.
75
);
CONSTANT
c_exp_w5_r2_signed_truncate
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w5_r2_signed_round_half_away
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
-4
,
-4
);
CONSTANT
c_exp_w5_r2_signed_round_half_away_clip
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w5_r2_signed_round_half_even
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
-4
,
-4
);
CONSTANT
c_exp_w5_r2_signed_round_half_even_clip
:
t_integer_arr
(
0
TO
31
)
:
=
(
-4
,
-4
,
-4
,
-3
,
-3
,
-3
,
-2
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w5_r2_unsigned_fixed_point
:
t_real_arr
(
0
TO
31
)
:
=
(
0
.
0
,
0
.
25
,
0
.
5
,
0
.
75
,
1
.
0
,
1
.
25
,
1
.
5
,
1
.
75
,
2
.
0
,
2
.
25
,
2
.
5
,
2
.
75
,
3
.
0
,
3
.
25
,
3
.
5
,
3
.
75
,
4
.
0
,
4
.
25
,
4
.
5
,
4
.
75
,
5
.
0
,
5
.
25
,
5
.
5
,
5
.
75
,
6
.
0
,
6
.
25
,
6
.
5
,
6
.
75
,
7
.
0
,
7
.
25
,
7
.
5
,
7
.
75
);
CONSTANT
c_exp_w5_r2_unsigned_truncate
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
);
CONSTANT
c_exp_w5_r2_unsigned_round_half_up
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
,
0
,
0
);
CONSTANT
c_exp_w5_r2_unsigned_round_half_up_clip
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
,
7
,
7
);
CONSTANT
c_exp_w5_r2_unsigned_round_half_even
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
0
,
0
);
CONSTANT
c_exp_w5_r2_unsigned_round_half_even_clip
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
,
7
);
-- Expected rounded results from [2] for w = g_in_dat_w = 5 and r = c_round_w = 3
CONSTANT
c_exp_w5_r3_sreal_fixed_point
:
t_real_arr
(
0
TO
31
)
:
=
(
-2
.
0
,
-1
.
875
,
-1
.
75
,
-1
.
625
,
-1
.
5
,
-1
.
375
,
-1
.
25
,
-1
.
125
,
-1
.
0
,
-0
.
875
,
-0
.
75
,
-0
.
625
,
-0
.
5
,
-0
.
375
,
-0
.
25
,
-0
.
125
,
0
.
0
,
0
.
125
,
0
.
25
,
0
.
375
,
0
.
5
,
0
.
625
,
0
.
75
,
0
.
875
,
1
.
0
,
1
.
125
,
1
.
25
,
1
.
375
,
1
.
5
,
1
.
625
,
1
.
75
,
1
.
875
);
CONSTANT
c_exp_w5_r3_signed_truncate
:
t_integer_arr
(
0
TO
31
)
:
=
(
-2
,
-2
,
-2
,
-2
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
);
CONSTANT
c_exp_w5_r3_signed_round_half_away
:
t_integer_arr
(
0
TO
31
)
:
=
(
-2
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
-2
,
-2
,
-2
,
-2
);
CONSTANT
c_exp_w5_r3_signed_round_half_away_clip
:
t_integer_arr
(
0
TO
31
)
:
=
(
-2
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
);
CONSTANT
c_exp_w5_r3_signed_round_half_even
:
t_integer_arr
(
0
TO
31
)
:
=
(
-2
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
-2
,
-2
,
-2
,
-2
);
CONSTANT
c_exp_w5_r3_signed_round_half_even_clip
:
t_integer_arr
(
0
TO
31
)
:
=
(
-2
,
-2
,
-2
,
-2
,
-2
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
-1
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
);
CONSTANT
c_exp_w5_r3_unsigned_fixed_point
:
t_real_arr
(
0
TO
31
)
:
=
(
0
.
0
,
0
.
125
,
0
.
25
,
0
.
375
,
0
.
5
,
0
.
625
,
0
.
75
,
0
.
875
,
1
.
0
,
1
.
125
,
1
.
25
,
1
.
375
,
1
.
5
,
1
.
625
,
1
.
75
,
1
.
875
,
2
.
0
,
2
.
125
,
2
.
25
,
2
.
375
,
2
.
5
,
2
.
625
,
2
.
75
,
2
.
875
,
3
.
0
,
3
.
125
,
3
.
25
,
3
.
375
,
3
.
5
,
3
.
625
,
3
.
75
,
3
.
875
);
CONSTANT
c_exp_w5_r3_unsigned_truncate
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w5_r3_unsigned_round_half_up
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
0
,
0
,
0
,
0
);
CONSTANT
c_exp_w5_r3_unsigned_round_half_up_clip
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
);
CONSTANT
c_exp_w5_r3_unsigned_round_half_even
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
0
,
0
,
0
,
0
);
CONSTANT
c_exp_w5_r3_unsigned_round_half_even_clip
:
t_natural_arr
(
0
TO
31
)
:
=
(
0
,
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
,
3
);
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
SIGNAL
clk
:
STD_LOGIC
:
=
'1'
;
...
...
@@ -91,7 +140,7 @@ ARCHITECTURE tb OF tb_round IS
SIGNAL
in_dat
:
STD_LOGIC_VECTOR
(
g_in_dat_w
-1
DOWNTO
0
);
SIGNAL
reg_val
:
STD_LOGIC
;
SIGNAL
reg_dat
:
STD_LOGIC_VECTOR
(
g_in_dat_w
-1
DOWNTO
0
);
-- Signed output data
-- . view as radix decimal in Wave window
SIGNAL
fs_signed_integer
:
STD_LOGIC_VECTOR
(
g_in_dat_w
-1
DOWNTO
0
);
...
...
@@ -101,20 +150,38 @@ ARCHITECTURE tb OF tb_round IS
SIGNAL
fs_signed_round_half_even
:
STD_LOGIC_VECTOR
(
g_out_dat_w
-1
DOWNTO
0
);
SIGNAL
fs_signed_round_half_even_clip
:
STD_LOGIC_VECTOR
(
g_out_dat_w
-1
DOWNTO
0
);
SIGNAL
S_w4
_r1
:
NATURAL
;
-- lookup index for signed
SIGNAL
S_w4
:
NATURAL
;
-- lookup index for signed
SIGNAL
exp_w4_r1_signed_truncate
:
INTEGER
;
SIGNAL
exp_w4_r1_signed_round_half_away
:
INTEGER
;
SIGNAL
exp_w4_r1_signed_round_half_away_clip
:
INTEGER
;
SIGNAL
exp_w4_r1_signed_round_half_even
:
INTEGER
;
SIGNAL
exp_w4_r1_signed_round_half_even_clip
:
INTEGER
;
SIGNAL
S_w5_r2
:
NATURAL
;
-- lookup index for signed
SIGNAL
exp_w4_r2_signed_truncate
:
INTEGER
;
SIGNAL
exp_w4_r2_signed_round_half_away
:
INTEGER
;
SIGNAL
exp_w4_r2_signed_round_half_away_clip
:
INTEGER
;
SIGNAL
exp_w4_r2_signed_round_half_even
:
INTEGER
;
SIGNAL
exp_w4_r2_signed_round_half_even_clip
:
INTEGER
;
SIGNAL
exp_w4_r3_signed_truncate
:
INTEGER
;
SIGNAL
exp_w4_r3_signed_round_half_away
:
INTEGER
;
SIGNAL
exp_w4_r3_signed_round_half_away_clip
:
INTEGER
;
SIGNAL
exp_w4_r3_signed_round_half_even
:
INTEGER
;
SIGNAL
exp_w4_r3_signed_round_half_even_clip
:
INTEGER
;
SIGNAL
S_w5
:
NATURAL
;
-- lookup index for signed
SIGNAL
exp_w5_r2_signed_truncate
:
INTEGER
;
SIGNAL
exp_w5_r2_signed_round_half_away
:
INTEGER
;
SIGNAL
exp_w5_r2_signed_round_half_away_clip
:
INTEGER
;
SIGNAL
exp_w5_r2_signed_round_half_even
:
INTEGER
;
SIGNAL
exp_w5_r2_signed_round_half_even_clip
:
INTEGER
;
SIGNAL
exp_w5_r3_signed_truncate
:
INTEGER
;
SIGNAL
exp_w5_r3_signed_round_half_away
:
INTEGER
;
SIGNAL
exp_w5_r3_signed_round_half_away_clip
:
INTEGER
;
SIGNAL
exp_w5_r3_signed_round_half_even
:
INTEGER
;
SIGNAL
exp_w5_r3_signed_round_half_even_clip
:
INTEGER
;
-- . show as real in Wave window
SIGNAL
fs_sreal_fixed_point
:
REAL
:
=
0
.
0
;
SIGNAL
fs_sreal_truncate
:
REAL
:
=
0
.
0
;
...
...
@@ -132,20 +199,38 @@ ARCHITECTURE tb OF tb_round IS
SIGNAL
fs_unsigned_round_half_even
:
STD_LOGIC_VECTOR
(
g_out_dat_w
-1
DOWNTO
0
);
SIGNAL
fs_unsigned_round_half_even_clip
:
STD_LOGIC_VECTOR
(
g_out_dat_w
-1
DOWNTO
0
);
SIGNAL
U_w4
_r1
:
NATURAL
;
-- lookup index for unsigned
SIGNAL
U_w4
:
NATURAL
;
-- lookup index for unsigned
SIGNAL
exp_w4_r1_unsigned_truncate
:
INTEGER
;
SIGNAL
exp_w4_r1_unsigned_round_half_up
:
INTEGER
;
SIGNAL
exp_w4_r1_unsigned_round_half_up_clip
:
INTEGER
;
SIGNAL
exp_w4_r1_unsigned_round_half_even
:
INTEGER
;
SIGNAL
exp_w4_r1_unsigned_round_half_even_clip
:
INTEGER
;
SIGNAL
U_w5_r2
:
NATURAL
;
-- lookup index for unsigned
SIGNAL
exp_w4_r2_unsigned_truncate
:
INTEGER
;
SIGNAL
exp_w4_r2_unsigned_round_half_up
:
INTEGER
;
SIGNAL
exp_w4_r2_unsigned_round_half_up_clip
:
INTEGER
;
SIGNAL
exp_w4_r2_unsigned_round_half_even
:
INTEGER
;
SIGNAL
exp_w4_r2_unsigned_round_half_even_clip
:
INTEGER
;
SIGNAL
exp_w4_r3_unsigned_truncate
:
INTEGER
;
SIGNAL
exp_w4_r3_unsigned_round_half_up
:
INTEGER
;
SIGNAL
exp_w4_r3_unsigned_round_half_up_clip
:
INTEGER
;
SIGNAL
exp_w4_r3_unsigned_round_half_even
:
INTEGER
;
SIGNAL
exp_w4_r3_unsigned_round_half_even_clip
:
INTEGER
;
SIGNAL
U_w5
:
NATURAL
;
-- lookup index for unsigned
SIGNAL
exp_w5_r2_unsigned_truncate
:
INTEGER
;
SIGNAL
exp_w5_r2_unsigned_round_half_up
:
INTEGER
;
SIGNAL
exp_w5_r2_unsigned_round_half_up_clip
:
INTEGER
;
SIGNAL
exp_w5_r2_unsigned_round_half_even
:
INTEGER
;
SIGNAL
exp_w5_r2_unsigned_round_half_even_clip
:
INTEGER
;
SIGNAL
exp_w5_r3_unsigned_truncate
:
INTEGER
;
SIGNAL
exp_w5_r3_unsigned_round_half_up
:
INTEGER
;
SIGNAL
exp_w5_r3_unsigned_round_half_up_clip
:
INTEGER
;
SIGNAL
exp_w5_r3_unsigned_round_half_even
:
INTEGER
;
SIGNAL
exp_w5_r3_unsigned_round_half_even_clip
:
INTEGER
;
-- . show as real in Wave window
SIGNAL
fs_ureal_fixed_point
:
REAL
:
=
0
.
0
;
SIGNAL
fs_ureal_truncate
:
REAL
:
=
0
.
0
;
...
...
@@ -376,31 +461,78 @@ BEGIN
fs_ureal_round_half_even_clip
<=
TO_UREAL
(
fs_unsigned_round_half_even_clip
,
0
);
-- Expected rounded values
S_w4_r1
<=
(
TO_UINT
(
in_dat
)
+
8
)
MOD
16
;
-- 2**4 = 16
exp_w4_r1_signed_truncate
<=
c_exp_w4_r1_signed_truncate
(
S_w4_r1
);
exp_w4_r1_signed_round_half_away
<=
c_exp_w4_r1_signed_round_half_away
(
S_w4_r1
);
exp_w4_r1_signed_round_half_away_clip
<=
c_exp_w4_r1_signed_round_half_away_clip
(
S_w4_r1
);
exp_w4_r1_signed_round_half_even
<=
c_exp_w4_r1_signed_round_half_even
(
S_w4_r1
);
exp_w4_r1_signed_round_half_even_clip
<=
c_exp_w4_r1_signed_round_half_even_clip
(
S_w4_r1
);
U_w4_r1
<=
TO_UINT
(
in_dat
)
MOD
16
;
exp_w4_r1_unsigned_truncate
<=
c_exp_w4_r1_unsigned_truncate
(
U_w4_r1
);
exp_w4_r1_unsigned_round_half_up
<=
c_exp_w4_r1_unsigned_round_half_up
(
U_w4_r1
);
exp_w4_r1_unsigned_round_half_up_clip
<=
c_exp_w4_r1_unsigned_round_half_up_clip
(
U_w4_r1
);
exp_w4_r1_unsigned_round_half_even
<=
c_exp_w4_r1_unsigned_round_half_even
(
U_w4_r1
);
exp_w4_r1_unsigned_round_half_even_clip
<=
c_exp_w4_r1_unsigned_round_half_even_clip
(
U_w4_r1
);
S_w5_r2
<=
(
TO_UINT
(
in_dat
)
+
16
)
MOD
32
;
-- 2**5 = 32
exp_w5_r2_signed_truncate
<=
c_exp_w5_r2_signed_truncate
(
S_w5_r2
);
exp_w5_r2_signed_round_half_away
<=
c_exp_w5_r2_signed_round_half_away
(
S_w5_r2
);
exp_w5_r2_signed_round_half_away_clip
<=
c_exp_w5_r2_signed_round_half_away_clip
(
S_w5_r2
);
exp_w5_r2_signed_round_half_even
<=
c_exp_w5_r2_signed_round_half_even
(
S_w5_r2
);
exp_w5_r2_signed_round_half_even_clip
<=
c_exp_w5_r2_signed_round_half_even_clip
(
S_w5_r2
);
U_w5_r2
<=
TO_UINT
(
in_dat
)
MOD
32
;
exp_w5_r2_unsigned_truncate
<=
c_exp_w5_r2_unsigned_truncate
(
U_w5_r2
);
exp_w5_r2_unsigned_round_half_up
<=
c_exp_w5_r2_unsigned_round_half_up
(
U_w5_r2
);
exp_w5_r2_unsigned_round_half_up_clip
<=
c_exp_w5_r2_unsigned_round_half_up_clip
(
U_w5_r2
);
exp_w5_r2_unsigned_round_half_even
<=
c_exp_w5_r2_unsigned_round_half_even
(
U_w5_r2
);
exp_w5_r2_unsigned_round_half_even_clip
<=
c_exp_w5_r2_unsigned_round_half_even_clip
(
U_w5_r2
);
-- . w = 4
S_w4
<=
(
TO_UINT
(
in_dat
)
+
8
)
MOD
16
;
-- 2**4 = 16
U_w4
<=
TO_UINT
(
in_dat
)
MOD
16
;
-- . w = 4, r = 1
exp_w4_r1_signed_truncate
<=
c_exp_w4_r1_signed_truncate
(
S_w4
);
exp_w4_r1_signed_round_half_away
<=
c_exp_w4_r1_signed_round_half_away
(
S_w4
);
exp_w4_r1_signed_round_half_away_clip
<=
c_exp_w4_r1_signed_round_half_away_clip
(
S_w4
);
exp_w4_r1_signed_round_half_even
<=
c_exp_w4_r1_signed_round_half_even
(
S_w4
);
exp_w4_r1_signed_round_half_even_clip
<=
c_exp_w4_r1_signed_round_half_even_clip
(
S_w4
);
exp_w4_r1_unsigned_truncate
<=
c_exp_w4_r1_unsigned_truncate
(
U_w4
);
exp_w4_r1_unsigned_round_half_up
<=
c_exp_w4_r1_unsigned_round_half_up
(
U_w4
);
exp_w4_r1_unsigned_round_half_up_clip
<=
c_exp_w4_r1_unsigned_round_half_up_clip
(
U_w4
);
exp_w4_r1_unsigned_round_half_even
<=
c_exp_w4_r1_unsigned_round_half_even
(
U_w4
);
exp_w4_r1_unsigned_round_half_even_clip
<=
c_exp_w4_r1_unsigned_round_half_even_clip
(
U_w4
);
-- . w = 4, r = 2
exp_w4_r2_signed_truncate
<=
c_exp_w4_r2_signed_truncate
(
S_w4
);
exp_w4_r2_signed_round_half_away
<=
c_exp_w4_r2_signed_round_half_away
(
S_w4
);
exp_w4_r2_signed_round_half_away_clip
<=
c_exp_w4_r2_signed_round_half_away_clip
(
S_w4
);
exp_w4_r2_signed_round_half_even
<=
c_exp_w4_r2_signed_round_half_even
(
S_w4
);
exp_w4_r2_signed_round_half_even_clip
<=
c_exp_w4_r2_signed_round_half_even_clip
(
S_w4
);
exp_w4_r2_unsigned_truncate
<=
c_exp_w4_r2_unsigned_truncate
(
U_w4
);
exp_w4_r2_unsigned_round_half_up
<=
c_exp_w4_r2_unsigned_round_half_up
(
U_w4
);
exp_w4_r2_unsigned_round_half_up_clip
<=
c_exp_w4_r2_unsigned_round_half_up_clip
(
U_w4
);
exp_w4_r2_unsigned_round_half_even
<=
c_exp_w4_r2_unsigned_round_half_even
(
U_w4
);
exp_w4_r2_unsigned_round_half_even_clip
<=
c_exp_w4_r2_unsigned_round_half_even_clip
(
U_w4
);
-- . w = 4, r = 3
exp_w4_r3_signed_truncate
<=
c_exp_w4_r3_signed_truncate
(
S_w4
);
exp_w4_r3_signed_round_half_away
<=
c_exp_w4_r3_signed_round_half_away
(
S_w4
);
exp_w4_r3_signed_round_half_away_clip
<=
c_exp_w4_r3_signed_round_half_away_clip
(
S_w4
);
exp_w4_r3_signed_round_half_even
<=
c_exp_w4_r3_signed_round_half_even
(
S_w4
);
exp_w4_r3_signed_round_half_even_clip
<=
c_exp_w4_r3_signed_round_half_even_clip
(
S_w4
);
exp_w4_r3_unsigned_truncate
<=
c_exp_w4_r3_unsigned_truncate
(
U_w4
);
exp_w4_r3_unsigned_round_half_up
<=
c_exp_w4_r3_unsigned_round_half_up
(
U_w4
);
exp_w4_r3_unsigned_round_half_up_clip
<=
c_exp_w4_r3_unsigned_round_half_up_clip
(
U_w4
);
exp_w4_r3_unsigned_round_half_even
<=
c_exp_w4_r3_unsigned_round_half_even
(
U_w4
);
exp_w4_r3_unsigned_round_half_even_clip
<=
c_exp_w4_r3_unsigned_round_half_even_clip
(
U_w4
);
-- . w = 5
S_w5
<=
(
TO_UINT
(
in_dat
)
+
16
)
MOD
32
;
-- 2**5 = 32
U_w5
<=
TO_UINT
(
in_dat
)
MOD
32
;
-- . w = 5, r = 2
exp_w5_r2_signed_truncate
<=
c_exp_w5_r2_signed_truncate
(
S_w5
);
exp_w5_r2_signed_round_half_away
<=
c_exp_w5_r2_signed_round_half_away
(
S_w5
);
exp_w5_r2_signed_round_half_away_clip
<=
c_exp_w5_r2_signed_round_half_away_clip
(
S_w5
);
exp_w5_r2_signed_round_half_even
<=
c_exp_w5_r2_signed_round_half_even
(
S_w5
);
exp_w5_r2_signed_round_half_even_clip
<=
c_exp_w5_r2_signed_round_half_even_clip
(
S_w5
);
exp_w5_r2_unsigned_truncate
<=
c_exp_w5_r2_unsigned_truncate
(
U_w5
);
exp_w5_r2_unsigned_round_half_up
<=
c_exp_w5_r2_unsigned_round_half_up
(
U_w5
);
exp_w5_r2_unsigned_round_half_up_clip
<=
c_exp_w5_r2_unsigned_round_half_up_clip
(
U_w5
);
exp_w5_r2_unsigned_round_half_even
<=
c_exp_w5_r2_unsigned_round_half_even
(
U_w5
);
exp_w5_r2_unsigned_round_half_even_clip
<=
c_exp_w5_r2_unsigned_round_half_even_clip
(
U_w5
);
-- . w = 5, r = 3
exp_w5_r3_signed_truncate
<=
c_exp_w5_r3_signed_truncate
(
S_w5
);
exp_w5_r3_signed_round_half_away
<=
c_exp_w5_r3_signed_round_half_away
(
S_w5
);
exp_w5_r3_signed_round_half_away_clip
<=
c_exp_w5_r3_signed_round_half_away_clip
(
S_w5
);
exp_w5_r3_signed_round_half_even
<=
c_exp_w5_r3_signed_round_half_even
(
S_w5
);
exp_w5_r3_signed_round_half_even_clip
<=
c_exp_w5_r3_signed_round_half_even_clip
(
S_w5
);
exp_w5_r3_unsigned_truncate
<=
c_exp_w5_r3_unsigned_truncate
(
U_w5
);
exp_w5_r3_unsigned_round_half_up
<=
c_exp_w5_r3_unsigned_round_half_up
(
U_w5
);
exp_w5_r3_unsigned_round_half_up_clip
<=
c_exp_w5_r3_unsigned_round_half_up_clip
(
U_w5
);
exp_w5_r3_unsigned_round_half_even
<=
c_exp_w5_r3_unsigned_round_half_even
(
U_w5
);
exp_w5_r3_unsigned_round_half_even_clip
<=
c_exp_w5_r3_unsigned_round_half_even_clip
(
U_w5
);
-- Verification
p_verify
:
PROCESS
...
...
@@ -437,6 +569,34 @@ BEGIN
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even
)
=
exp_w4_r1_unsigned_round_half_even
REPORT
"Wrong exp_w4_r1_unsigned_round_half_even"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even_clip
)
=
exp_w4_r1_unsigned_round_half_even_clip
REPORT
"Wrong exp_w4_r1_unsigned_round_half_even_clip"
SEVERITY
ERROR
;
END
IF
;
IF
g_in_dat_w
=
4
AND
c_round_w
=
2
THEN
-- . signed
ASSERT
SIGNED
(
fs_signed_truncate
)
=
exp_w4_r2_signed_truncate
REPORT
"Wrong exp_w4_r2_signed_truncate"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_away
)
=
exp_w4_r2_signed_round_half_away
REPORT
"Wrong exp_w4_r2_signed_round_half_away"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_away_clip
)
=
exp_w4_r2_signed_round_half_away_clip
REPORT
"Wrong exp_w4_r2_signed_round_half_away_clip"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_even
)
=
exp_w4_r2_signed_round_half_even
REPORT
"Wrong exp_w4_r2_signed_round_half_even"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_even_clip
)
=
exp_w4_r2_signed_round_half_even_clip
REPORT
"Wrong exp_w4_r2_signed_round_half_even_clip"
SEVERITY
ERROR
;
-- . unsigned
ASSERT
UNSIGNED
(
fs_unsigned_truncate
)
=
exp_w4_r2_unsigned_truncate
REPORT
"Wrong exp_w4_r2_unsigned_truncate"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_up
)
=
exp_w4_r2_unsigned_round_half_up
REPORT
"Wrong exp_w4_r2_unsigned_round_half_up"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_up_clip
)
=
exp_w4_r2_unsigned_round_half_up_clip
REPORT
"Wrong exp_w4_r2_unsigned_round_half_up_clip"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even
)
=
exp_w4_r2_unsigned_round_half_even
REPORT
"Wrong exp_w4_r2_unsigned_round_half_even"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even_clip
)
=
exp_w4_r2_unsigned_round_half_even_clip
REPORT
"Wrong exp_w4_r2_unsigned_round_half_even_clip"
SEVERITY
ERROR
;
END
IF
;
IF
g_in_dat_w
=
4
AND
c_round_w
=
3
THEN
-- . signed
ASSERT
SIGNED
(
fs_signed_truncate
)
=
exp_w4_r3_signed_truncate
REPORT
"Wrong exp_w4_r3_signed_truncate"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_away
)
=
exp_w4_r3_signed_round_half_away
REPORT
"Wrong exp_w4_r3_signed_round_half_away"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_away_clip
)
=
exp_w4_r3_signed_round_half_away_clip
REPORT
"Wrong exp_w4_r3_signed_round_half_away_clip"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_even
)
=
exp_w4_r3_signed_round_half_even
REPORT
"Wrong exp_w4_r3_signed_round_half_even"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_even_clip
)
=
exp_w4_r3_signed_round_half_even_clip
REPORT
"Wrong exp_w4_r3_signed_round_half_even_clip"
SEVERITY
ERROR
;
-- . unsigned
ASSERT
UNSIGNED
(
fs_unsigned_truncate
)
=
exp_w4_r3_unsigned_truncate
REPORT
"Wrong exp_w4_r3_unsigned_truncate"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_up
)
=
exp_w4_r3_unsigned_round_half_up
REPORT
"Wrong exp_w4_r3_unsigned_round_half_up"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_up_clip
)
=
exp_w4_r3_unsigned_round_half_up_clip
REPORT
"Wrong exp_w4_r3_unsigned_round_half_up_clip"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even
)
=
exp_w4_r3_unsigned_round_half_even
REPORT
"Wrong exp_w4_r3_unsigned_round_half_even"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even_clip
)
=
exp_w4_r3_unsigned_round_half_even_clip
REPORT
"Wrong exp_w4_r3_unsigned_round_half_even_clip"
SEVERITY
ERROR
;
END
IF
;
IF
g_in_dat_w
=
5
AND
c_round_w
=
2
THEN
-- . signed
ASSERT
SIGNED
(
fs_signed_truncate
)
=
exp_w5_r2_signed_truncate
REPORT
"Wrong exp_w5_r2_signed_truncate"
SEVERITY
ERROR
;
...
...
@@ -451,6 +611,20 @@ BEGIN
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even
)
=
exp_w5_r2_unsigned_round_half_even
REPORT
"Wrong exp_w5_r2_unsigned_round_half_even"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even_clip
)
=
exp_w5_r2_unsigned_round_half_even_clip
REPORT
"Wrong exp_w5_r2_unsigned_round_half_even_clip"
SEVERITY
ERROR
;
END
IF
;
IF
g_in_dat_w
=
5
AND
c_round_w
=
3
THEN
-- . signed
ASSERT
SIGNED
(
fs_signed_truncate
)
=
exp_w5_r3_signed_truncate
REPORT
"Wrong exp_w5_r3_signed_truncate"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_away
)
=
exp_w5_r3_signed_round_half_away
REPORT
"Wrong exp_w5_r3_signed_round_half_away"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_away_clip
)
=
exp_w5_r3_signed_round_half_away_clip
REPORT
"Wrong exp_w5_r3_signed_round_half_away_clip"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_even
)
=
exp_w5_r3_signed_round_half_even
REPORT
"Wrong exp_w5_r3_signed_round_half_even"
SEVERITY
ERROR
;
ASSERT
SIGNED
(
fs_signed_round_half_even_clip
)
=
exp_w5_r3_signed_round_half_even_clip
REPORT
"Wrong exp_w5_r3_signed_round_half_even_clip"
SEVERITY
ERROR
;
-- . unsigned
ASSERT
UNSIGNED
(
fs_unsigned_truncate
)
=
exp_w5_r3_unsigned_truncate
REPORT
"Wrong exp_w5_r3_unsigned_truncate"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_up
)
=
exp_w5_r3_unsigned_round_half_up
REPORT
"Wrong exp_w5_r3_unsigned_round_half_up"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_up_clip
)
=
exp_w5_r3_unsigned_round_half_up_clip
REPORT
"Wrong exp_w5_r3_unsigned_round_half_up_clip"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even
)
=
exp_w5_r3_unsigned_round_half_even
REPORT
"Wrong exp_w5_r3_unsigned_round_half_even"
SEVERITY
ERROR
;
ASSERT
UNSIGNED
(
fs_unsigned_round_half_even_clip
)
=
exp_w5_r3_unsigned_round_half_even_clip
REPORT
"Wrong exp_w5_r3_unsigned_round_half_even_clip"
SEVERITY
ERROR
;
END
IF
;
END
IF
;
END
IF
;
END
PROCESS
;
...
...
This diff is collapsed.
Click to expand it.
libraries/base/common/tb/vhdl/tb_tb_round.vhd
+
3
−
0
View file @
6e612423
...
...
@@ -35,5 +35,8 @@ BEGIN
u_extend
:
ENTITY
work
.
tb_round
GENERIC
MAP
(
5
,
6
);
u_wires
:
ENTITY
work
.
tb_round
GENERIC
MAP
(
5
,
5
);
u_round_w4_r1
:
ENTITY
work
.
tb_round
GENERIC
MAP
(
4
,
3
);
-- -r = 4 - 3 = 1
u_round_w4_r2
:
ENTITY
work
.
tb_round
GENERIC
MAP
(
4
,
2
);
-- -r = 4 - 2 = 2
u_round_w4_r3
:
ENTITY
work
.
tb_round
GENERIC
MAP
(
4
,
1
);
-- -r = 4 - 1 = 3
u_round_w5_r2
:
ENTITY
work
.
tb_round
GENERIC
MAP
(
5
,
3
);
-- -r = 5 - 3 = 2
u_round_w5_r3
:
ENTITY
work
.
tb_round
GENERIC
MAP
(
5
,
2
);
-- -r = 5 - 2 = 3
END
tb
;
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