Use separate g_in_rst_level.

libraries/base/common/src/vhdl/common_areset.vhd

@@ -19,11 +19,18 @@
 --
 -------------------------------------------------------------------------------
 
-
+-- Author: E. Kooistra
 -- Purpose: Immediately apply reset and synchronously release it at rising clk
 -- Description:
---   Using common_areset is equivalent to using common_async with same signal
---   applied to rst and din.
+--   When in_rst gets asserted, then the out_rst gets asserted immediately (= asynchronous reset apply).
+--   When in_rst gets de-assered, then out_rst gets de-asserted after g_delay_len cycles (= synchronous reset release).
+--
+--   The in_rst assert level is set by g_in_rst_level.
+--   The out_rst assert level is set by c_out_rst_level = g_rst_level.
+--
+-- Remarks:
+-- . The in_rst can also synchronise other signals than a reset, e.g. a locked signal from a PLL.
+
 
 LIBRARY IEEE;
 USE IEEE.std_logic_1164.ALL;
@@ -31,7 +38,9 @@ USE work.common_pkg.ALL;
 
 ENTITY common_areset IS
   GENERIC (
-    g_rst_level : STD_LOGIC := '1';
+    g_in_rst_level : STD_LOGIC := '1';  -- = in_rst level
+    g_rst_level    : STD_LOGIC := '1';  -- = out_rst level (keep original generic
+                                        --   name for backward compatibility)
     g_delay_len    : NATURAL   := c_meta_delay_len
   );
   PORT (
@@ -44,27 +53,24 @@ END;
 
 ARCHITECTURE str OF common_areset IS
  
-  CONSTANT c_rst_level_n : STD_LOGIC := NOT g_rst_level;
+  CONSTANT c_out_rst_level   : STD_LOGIC := g_rst_level;
+  CONSTANT c_out_rst_level_n : STD_LOGIC := NOT g_rst_level;
+
   SIGNAL i_rst               : STD_LOGIC;
-BEGIN
 
-  -- When in_rst becomes g_rst_level then out_rst follows immediately (asynchronous reset apply).
-  -- When in_rst becomes NOT g_rst_level then out_rst follows after g_delay_len cycles (synchronous reset release).
+BEGIN
 
-  -- This block can also synchronise other signals than reset:
-  -- . g_rst_level = '0': output asynchronoulsy follows the falling edge input and synchronises the rising edge input.
-  -- . g_rst_level = '1': output asynchronoulsy follows the rising edge input and synchronises the falling edge input.
+  i_rst <= in_rst WHEN g_in_rst_level = '1' ELSE NOT in_rst;
 
-  i_rst <= NOT in_rst WHEN g_rst_level = '0' ELSE in_rst;
   u_async : ENTITY work.common_async
   GENERIC MAP (
-    g_rst_level => g_rst_level,
+    g_rst_level => c_out_rst_level,
     g_delay_len => g_delay_len
   )
   PORT MAP (
     rst  => i_rst,
     clk  => clk,
-    din  => c_rst_level_n,
+    din  => c_out_rst_level_n,
     dout => out_rst
   );