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Commit 6d969ed3 authored by Eric Kooistra's avatar Eric Kooistra
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Improved generic naming, use c_buffer_nof_blocks as constant, worked on tb.

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1 merge request!156Added first version of dp_bsn_align_v2.vhd with mmp and tb. This was...
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libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
+ 5
− 7
View file @ 6d969ed3
...@@ -45,12 +45,11 @@ ENTITY mmp_dp_bsn_align_v2 IS ...@@ -45,12 +45,11 @@ ENTITY mmp_dp_bsn_align_v2 IS
GENERIC ( GENERIC (
g_nof_streams : NATURAL; -- number of input and output streams g_nof_streams : NATURAL; -- number of input and output streams
g_bsn_latency_max : NATURAL; -- Maximum travel latency of a remote block in number of block periods T_blk g_bsn_latency_max : NATURAL; -- Maximum travel latency of a remote block in number of block periods T_blk
g_bsn_latency_use_node_index : BOOLEAN := FALSE; -- FALSE for align at end node, TRUE for align at every intermediate node g_nof_aligners_max : NATURAL := 1; -- 1 when only align at last node, > 1 when align at every intermediate node
g_block_size : NATURAL := 32; -- > 1, g_block_size=1 is not supported g_block_size : NATURAL := 32; -- > 1, g_block_size=1 is not supported
g_buffer_nof_blocks : NATURAL; -- circular buffer size per input, choose ceil_pow2(1 + g_bsn_latency_max)
g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN
g_data_w : NATURAL; -- number of bits in sosi data g_data_w : NATURAL; -- number of bits in sosi data
g_filler_value : INTEGER := 0; -- output sosi data value for missing input blocks g_replacement_value : INTEGER := 0; -- output sosi data value for missing input blocks
g_nof_clk_per_sync : NATURAL := 200*10**6; g_nof_clk_per_sync : NATURAL := 200*10**6;
g_nof_input_bsn_monitors : NATURAL := 0; g_nof_input_bsn_monitors : NATURAL := 0;
g_use_bsn_output_monitor : BOOLEAN := FALSE g_use_bsn_output_monitor : BOOLEAN := FALSE
...@@ -73,7 +72,7 @@ ENTITY mmp_dp_bsn_align_v2 IS ...@@ -73,7 +72,7 @@ ENTITY mmp_dp_bsn_align_v2 IS
dp_rst : IN STD_LOGIC; dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC; dp_clk : IN STD_LOGIC;
node_index : IN NATURAL := 0; -- only used when g_bsn_latency_use_node_index is TRUE node_index : IN NATURAL := 0; -- only used when g_nof_aligners_max > 1
-- Streaming input -- Streaming input
in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
...@@ -197,12 +196,11 @@ BEGIN ...@@ -197,12 +196,11 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
g_nof_streams => g_nof_streams, g_nof_streams => g_nof_streams,
g_bsn_latency_max => g_bsn_latency_max, g_bsn_latency_max => g_bsn_latency_max,
g_bsn_latency_use_node_index => g_bsn_latency_use_node_index, g_nof_aligners_max => g_nof_aligners_max,
g_block_size => g_block_size, g_block_size => g_block_size,
g_buffer_nof_blocks => g_buffer_nof_blocks,
g_bsn_w => g_bsn_w, g_bsn_w => g_bsn_w,
g_data_w => g_data_w, g_data_w => g_data_w,
g_filler_value => g_filler_value g_replacement_value => g_replacement_value
) )
PORT MAP ( PORT MAP (
dp_rst => dp_rst, dp_rst => dp_rst,
......
libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
+ 51
− 200
View file @ 6d969ed3
...@@ -28,7 +28,7 @@ USE IEEE.std_logic_1164.ALL; ...@@ -28,7 +28,7 @@ USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL; USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL; USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_lfsr_sequences_pkg.ALL; USE common_lib.common_str_pkg.ALL;
USE common_lib.tb_common_pkg.ALL; USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL; USE dp_lib.tb_dp_pkg.ALL;
...@@ -38,20 +38,20 @@ ENTITY tb_dp_bsn_align_v2 IS ...@@ -38,20 +38,20 @@ ENTITY tb_dp_bsn_align_v2 IS
GENERIC ( GENERIC (
-- DUT -- DUT
g_nof_streams : NATURAL := 2; -- number of input and output streams g_nof_streams : NATURAL := 2; -- number of input and output streams
g_bsn_latency_max : NATURAL := 1; -- Maximum travel latency of a remote block in number of block periods T_blk g_bsn_latency_max : NATURAL := 2; -- Maximum travel latency of a remote block in number of block periods T_blk
g_bsn_latency_use_node_index : BOOLEAN := FALSE; -- FALSE for align at end node, TRUE for align at every intermediate node g_nof_aligners_max : POSITIVE := 1; -- 1 when only align at last node, > 1 when align at every intermediate node
g_block_size : NATURAL := 11; -- > 1, g_block_size=1 is not supported g_block_size : NATURAL := 11; -- > 1, g_block_size=1 is not supported
g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN
g_data_w : NATURAL := 16; -- number of bits in sosi data g_data_w : NATURAL := 16; -- number of bits in sosi data
g_filler_value : INTEGER := 0; -- output sosi data value for missing input blocks g_replacement_value : INTEGER := 17; -- output sosi data replacement value for missing input blocks
g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP
g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure
g_rd_latency : NATURAL := 2; -- 1 or 2, choose 2 to ease timing closure g_rd_latency : NATURAL := 2; -- 1 or 2, choose 2 to ease timing closure
-- TB -- TB
g_diff_delay : NATURAL := 0; g_diff_delay : NATURAL := 0; -- nof clk delay between inputs
g_diff_bsn : NATURAL := 0; -- g_diff_bsn = g_bsn_latency_max can just be aligned g_diff_bsn : NATURAL := 0; -- g_diff_bsn = g_bsn_latency_max can just be aligned
g_nof_repeat : NATURAL := 100 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli g_nof_repeat : NATURAL := 8
); );
END tb_dp_bsn_align_v2; END tb_dp_bsn_align_v2;
...@@ -59,8 +59,6 @@ END tb_dp_bsn_align_v2; ...@@ -59,8 +59,6 @@ END tb_dp_bsn_align_v2;
ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS
CONSTANT c_rl : NATURAL := 1; CONSTANT c_rl : NATURAL := 1;
CONSTANT c_pulse_active : NATURAL := 1;
CONSTANT c_pulse_period : NATURAL := 7;
CONSTANT c_data_w : NATURAL := 16; CONSTANT c_data_w : NATURAL := 16;
CONSTANT c_data_init : INTEGER := 0; CONSTANT c_data_init : INTEGER := 0;
...@@ -73,20 +71,11 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS ...@@ -73,20 +71,11 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS
CONSTANT c_gap_size : NATURAL := 10; CONSTANT c_gap_size : NATURAL := 10;
CONSTANT c_block_period : NATURAL := g_block_size + c_gap_size; CONSTANT c_block_period : NATURAL := g_block_size + c_gap_size;
CONSTANT c_xoff_timeout : NATURAL := c_block_period * g_bsn_latency_max * 2; -- xoff timeout to recover for next alignment attempt
CONSTANT c_sop_timeout : NATURAL := c_block_period * g_bsn_latency_max; -- sop timeout to end current aligment attempt
CONSTANT c_event_input : NATURAL := smallest(1, g_nof_streams-1); -- select special event input at which the event will apply, use >= g_nof_streams to disable the special events
CONSTANT c_buffer_nof_blocks : NATURAL := ceil_pow2(1 + g_bsn_latency_max); -- circular buffer size per input
TYPE t_data_arr IS ARRAY (g_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0); TYPE t_data_arr IS ARRAY (g_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
TYPE t_bsn_arr IS ARRAY (g_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0); TYPE t_bsn_arr IS ARRAY (g_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
TYPE t_err_arr IS ARRAY (g_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_dp_stream_error_w-1 DOWNTO 0); TYPE t_err_arr IS ARRAY (g_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_dp_stream_error_w-1 DOWNTO 0);
TYPE t_channel_arr IS ARRAY (g_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_dp_stream_channel_w-1 DOWNTO 0); TYPE t_channel_arr IS ARRAY (g_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_dp_stream_channel_w-1 DOWNTO 0);
TYPE t_rl_vec_arr IS ARRAY (g_nof_streams-1 DOWNTO 0) OF STD_LOGIC_VECTOR(0 TO c_rl);
TYPE t_tb_state IS (s_idle, s_bsn_mis_aligned, s_bsn_aligned, s_small_bsn_diff, s_large_bsn_diff, s_restore_bsn, s_disable_one_input, s_enable_inputs);
TYPE t_reg IS RECORD TYPE t_reg IS RECORD
-- p_write_arr -- p_write_arr
...@@ -95,15 +84,12 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS ...@@ -95,15 +84,12 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS
out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
END RECORD; END RECORD;
SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL tb_end_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL tb_end : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1'; SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '1'; SIGNAL rst : STD_LOGIC := '1';
SIGNAL sl1 : STD_LOGIC := '1'; SIGNAL sl1 : STD_LOGIC := '1';
SIGNAL random : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
SIGNAL pulse : STD_LOGIC;
SIGNAL pulse_en : STD_LOGIC := '1';
SIGNAL node_index : NATURAL := 0; SIGNAL node_index : NATURAL := 0;
SIGNAL in_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); SIGNAL in_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
...@@ -140,28 +126,18 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS ...@@ -140,28 +126,18 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS
SIGNAL out_err : t_err_arr; SIGNAL out_err : t_err_arr;
SIGNAL out_channel : t_channel_arr; SIGNAL out_channel : t_channel_arr;
SIGNAL tb_state : t_tb_state; SIGNAL in_sosi_arr_dly : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL out_sosi_arr_exp : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL tb_bsn : INTEGER;
SIGNAL verify_done_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL verify_done_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL default_end_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL default_end : STD_LOGIC;
SIGNAL verify_dis_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL verify_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL verify_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL hold_out_sop : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); SIGNAL hold_out_sop : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL prev_out_ready : t_rl_vec_arr;
SIGNAL prev_out_bsn : t_bsn_arr; SIGNAL prev_out_bsn : t_bsn_arr;
SIGNAL expected_out_bsn : t_bsn_arr; SIGNAL expected_out_bsn : t_bsn_arr;
SIGNAL prev_out_data : t_data_arr; SIGNAL prev_out_data : t_data_arr;
SIGNAL expected_out_data : t_data_arr; SIGNAL expected_out_data : t_data_arr;
SIGNAL verify_extra_end : STD_LOGIC := '0';
SIGNAL bsn_diff : INTEGER;
SIGNAL bsn_offset : INTEGER;
SIGNAL bsn_event : STD_LOGIC := '0'; -- pulse '1' triggers a BSN offset for an input
SIGNAL bsn_event_ack_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL bsn_event_ack : STD_LOGIC;
SIGNAL stream_en_event : STD_LOGIC := '0'; -- pulse '1' indicates that the stream enables in stream_en_arr have been updated
SIGNAL stream_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'1'); -- default all streams are enabled SIGNAL stream_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS=>'1'); -- default all streams are enabled
BEGIN BEGIN
...@@ -169,10 +145,6 @@ BEGIN ...@@ -169,10 +145,6 @@ BEGIN
clk <= (NOT clk) OR tb_end AFTER clk_period/2; clk <= (NOT clk) OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER clk_period*7; rst <= '1', '0' AFTER clk_period*7;
random <= func_common_random(random) WHEN rising_edge(clk);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period+1, '1', rst, clk, pulse_en, pulse);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- DATA GENERATION -- DATA GENERATION
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -194,10 +166,10 @@ BEGIN ...@@ -194,10 +166,10 @@ BEGIN
v_bsn := INCR_UVEC(v_bsn, v_diff_bsn); v_bsn := INCR_UVEC(v_bsn, v_diff_bsn);
in_sosi_arr(I) <= c_dp_sosi_rst; in_sosi_arr(I) <= c_dp_sosi_rst;
proc_common_wait_until_low(clk, rst); proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, c_xoff_timeout*2); proc_common_wait_some_cycles(clk, 10);
-- Create latency misalignment between the input streams -- Create latency misalignment between the input streams
proc_common_wait_some_cycles(clk, I*g_diff_delay/g_nof_streams); proc_common_wait_some_cycles(clk, I*g_diff_delay);
-- Begin of stimuli -- Begin of stimuli
FOR R IN 0 TO g_nof_repeat-v_diff_bsn-1 LOOP FOR R IN 0 TO g_nof_repeat-v_diff_bsn-1 LOOP
...@@ -208,172 +180,39 @@ BEGIN ...@@ -208,172 +180,39 @@ BEGIN
proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames
END LOOP; END LOOP;
-- End of default stimuli -- End of stimuli, g_bsn_latency_max blocks remain in buffer
expected_out_bsn(I) <= INCR_UVEC(v_bsn, -1); expected_out_bsn(I) <= INCR_UVEC(v_bsn, -1 -g_bsn_latency_max);
expected_out_data(I) <= TO_UVEC(v_data-1, c_data_w); expected_out_data(I) <= TO_UVEC(v_data-1 -g_bsn_latency_max*g_block_size, c_data_w);
proc_common_wait_some_cycles(clk, 100); -- depends on stream control proc_common_wait_some_cycles(clk, 100);
default_end_arr(I) <= '1';
verify_done_arr(I) <= '1'; verify_done_arr(I) <= '1';
proc_common_wait_some_cycles(clk, 1); proc_common_wait_some_cycles(clk, 1);
verify_done_arr(I) <= '0'; verify_done_arr(I) <= '0';
-------------------------------------------------------------------------- tb_end_arr(I) <= '1';
-- Extra
--------------------------------------------------------------------------
proc_common_wait_some_cycles(clk, 500);
WHILE verify_extra_end /= '1' LOOP
v_sync := sel_a_b(TO_UINT(v_bsn) MOD c_sync_period = c_sync_offset, '1', '0');
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, g_block_size, v_channel, v_err, v_sync, v_bsn, clk, stream_en_arr(I), in_siso_arr(I), in_sosi_arr(I));
v_bsn := INCR_UVEC(v_bsn, 1);
bsn_event_ack_arr(I) <= '0';
IF I=c_event_input AND bsn_event='1' THEN
v_bsn := INCR_UVEC(v_bsn, bsn_offset);
bsn_event_ack_arr(I) <= '1';
END IF;
v_data := v_data + g_block_size;
proc_common_wait_some_cycles(clk, c_gap_size); -- create gap between frames
END LOOP;
-- End of extra stimuli
expected_out_bsn(I) <= INCR_UVEC(v_bsn, -1);
expected_out_data(I) <= TO_UVEC(v_data-1, c_data_w);
verify_done_arr(I) <= '1';
proc_common_wait_some_cycles(clk, 1);
verify_done_arr(I) <= '0';
WAIT; WAIT;
END PROCESS; END PROCESS;
END GENERATE; END GENERATE;
default_end <= vector_and(default_end_arr); tb_end <= vector_and(tb_end_arr);
bsn_event_ack <= vector_or(bsn_event_ack_arr);
p_special_stimuli : PROCESS
BEGIN
verify_dis_arr <= (OTHERS=>'0');
tb_state <= s_bsn_mis_aligned;
stream_en_event <= '0';
stream_en_arr <= (OTHERS=>'1');
----------------------------------------------------------------------------
-- Wait until default verify test is done
----------------------------------------------------------------------------
proc_common_wait_until_high(clk, default_end);
verify_dis_arr <= (OTHERS=>'1');
proc_common_wait_some_cycles(clk, 100);
verify_dis_arr <= (OTHERS=>'0');
tb_state <= s_bsn_aligned;
proc_common_wait_some_cycles(clk, 1000);
----------------------------------------------------------------------------
-- Verify change in input BSN offset
----------------------------------------------------------------------------
-- . enforce small BSN misalignment
tb_state <= s_small_bsn_diff;
verify_dis_arr <= (OTHERS=>'1');
bsn_offset <= -1;
bsn_event <= '1';
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
proc_common_wait_some_cycles(clk, 100);
verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 1000);
verify_dis_arr <= (OTHERS=>'1');
-- . restore original BSN sequence
tb_state <= s_restore_bsn;
bsn_offset <= +1;
bsn_event <= '1';
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
proc_common_wait_some_cycles(clk, 100);
verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 1000);
-- verify_dis_arr <= (OTHERS=>'1');
-- . enforce large BSN misalignment
tb_state <= s_large_bsn_diff;
bsn_offset <= -g_bsn_latency_max-1;
bsn_event <= '1';
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
-- expect no output, because difference remains too large, so do not restart verify_en here and leave it commented:
-- proc_common_wait_some_cycles(clk, 100);
-- verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 1000);
verify_dis_arr <= (OTHERS=>'1');
-- . restore original BSN sequence
tb_state <= s_restore_bsn;
bsn_offset <= g_bsn_latency_max+1;
bsn_event <= '1';
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
proc_common_wait_some_cycles(clk, 100);
verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 1000);
----------------------------------------------------------------------------
-- Verify change in input enables
----------------------------------------------------------------------------
tb_state <= s_disable_one_input;
verify_dis_arr <= (OTHERS=>'1');
stream_en_event <= '1';
stream_en_arr(c_event_input) <= '0'; -- switch an input off
proc_common_wait_some_cycles(clk, 1);
stream_en_event <= '0';
proc_common_wait_some_cycles(clk, 100);
verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 2000); -- keep this input off for a while
tb_state <= s_enable_inputs;
verify_dis_arr <= (OTHERS=>'1');
stream_en_event <= '1';
stream_en_arr(c_event_input) <= '1'; -- switch this input on
proc_common_wait_some_cycles(clk, 1);
stream_en_event <= '0';
proc_common_wait_some_cycles(clk, 100);
verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 500);
tb_state <= s_restore_bsn;
verify_dis_arr <= (OTHERS=>'1');
bsn_offset <= bsn_diff; -- use input 0 to restore original BSN sequence for input c_event_input, that got lost due to input disable
bsn_event <= '1';
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
proc_common_wait_some_cycles(clk, 100);
verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 2000);
tb_state <= s_idle;
verify_extra_end <= '1';
proc_common_wait_some_cycles(clk, 500);
tb_end <= '1';
WAIT;
END PROCESS;
bsn_diff <= TO_UINT(in_sosi_arr(0).bsn) - TO_UINT(in_sosi_arr(c_event_input).bsn) WHEN rising_edge(clk) AND in_sosi_arr(0).sop='1';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- DATA VERIFICATION -- DATA VERIFICATION
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
gen_verify : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE tb_bsn <= TO_UINT(out_sosi_arr(0).bsn);
-- Verification logistics
verify_en_arr(I) <= '1' WHEN rising_edge(clk) AND verify_dis_arr(I)='0' AND stream_en_arr(I)='1' AND out_sosi_arr(I).sop='1' ELSE p_verify_en_arr : PROCESS
'0' WHEN rising_edge(clk) AND verify_dis_arr(I)='1'; -- verify enable after first output sop BEGIN
-- Skip initial blocks from verification
proc_common_wait_until_value(TO_UINT(c_bsn_init) + g_bsn_latency_max, clk, tb_bsn);
verify_en_arr <= (OTHERS => '1');
proc_common_wait_until_value(TO_UINT(c_bsn_init) + g_nof_repeat - g_bsn_latency_max - 1, clk, tb_bsn);
verify_en_arr <= (OTHERS => '0');
WAIT;
END PROCESS;
gen_verify_sosi : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE
-- Ease in_sosi_arr monitoring -- Ease in_sosi_arr monitoring
in_data(I) <= in_sosi_arr(I).data(c_data_w-1 DOWNTO 0); in_data(I) <= in_sosi_arr(I).data(c_data_w-1 DOWNTO 0);
in_val(I) <= in_sosi_arr(I).valid; in_val(I) <= in_sosi_arr(I).valid;
...@@ -395,8 +234,6 @@ BEGIN ...@@ -395,8 +234,6 @@ BEGIN
out_bsn(I) <= out_sosi_arr(I).bsn(c_bsn_w-1 DOWNTO 0); out_bsn(I) <= out_sosi_arr(I).bsn(c_bsn_w-1 DOWNTO 0);
-- Actual verification of the output streams -- Actual verification of the output streams
-- . Verify that the output valid fits with the output ready latency
proc_dp_verify_valid(c_rl, clk, verify_en_arr(I), out_siso_arr(I).ready, prev_out_ready(I), out_val(I));
-- . Verify that sop and eop come in pairs -- . Verify that sop and eop come in pairs
proc_dp_verify_sop_and_eop(clk, out_val(I), out_sop(I), out_eop(I), hold_out_sop(I)); proc_dp_verify_sop_and_eop(clk, out_val(I), out_sop(I), out_eop(I), hold_out_sop(I));
...@@ -409,6 +246,22 @@ BEGIN ...@@ -409,6 +246,22 @@ BEGIN
proc_dp_verify_value("out_bsn", e_equal, clk, verify_done_arr(I), expected_out_bsn(I), prev_out_bsn(I)); proc_dp_verify_value("out_bsn", e_equal, clk, verify_done_arr(I), expected_out_bsn(I), prev_out_bsn(I));
END GENERATE; END GENERATE;
in_sosi_arr_dly <= TRANSPORT in_sosi_arr AFTER (g_bsn_latency_max * (g_block_size + c_gap_size) + 5) * clk_period;
out_sosi_arr_exp <= in_sosi_arr_dly WHEN rising_edge(clk);
gen_verify_data : FOR I IN g_nof_streams-1 DOWNTO 0 GENERATE
p_verify_data : PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
IF verify_en_arr(I) = '1' AND out_sosi_arr_exp(I).valid = '1' THEN
ASSERT out_sosi_arr(I).valid = out_sosi_arr_exp(I).valid REPORT "Wrong valid for output " & int_to_str(I) SEVERITY ERROR;
ASSERT out_sosi_arr(I).data = out_sosi_arr_exp(I).data REPORT "Wrong data for output " & int_to_str(I) & " : "
& int_to_str(TO_UINT(out_sosi_arr(I).data))
& " /= " & int_to_str(TO_UINT(out_sosi_arr_exp(I).data)) SEVERITY ERROR;
END IF;
END IF;
END PROCESS;
END GENERATE;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- DUT -- DUT
...@@ -418,13 +271,11 @@ BEGIN ...@@ -418,13 +271,11 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
g_nof_streams => g_nof_streams, g_nof_streams => g_nof_streams,
g_bsn_latency_max => g_bsn_latency_max, g_bsn_latency_max => g_bsn_latency_max,
g_bsn_latency_use_node_index => g_bsn_latency_use_node_index, g_nof_aligners_max => g_nof_aligners_max,
g_node_index_max => 31, -- limit to functional 5 bit range, instead of full 31 bit NATURAL range
g_block_size => g_block_size, g_block_size => g_block_size,
g_buffer_nof_blocks => c_buffer_nof_blocks,
g_bsn_w => g_bsn_w, g_bsn_w => g_bsn_w,
g_data_w => g_data_w, g_data_w => g_data_w,
g_filler_value => g_filler_value, g_replacement_value => g_replacement_value,
g_use_mm_output => g_use_mm_output, -- output via MM or via streaming DP g_use_mm_output => g_use_mm_output, -- output via MM or via streaming DP
g_pipeline_input => g_pipeline_input, -- >= 0, choose 0 for wires, choose 1 to ease timing closure g_pipeline_input => g_pipeline_input, -- >= 0, choose 0 for wires, choose 1 to ease timing closure
g_rd_latency => g_rd_latency -- 1 or 2, choose 2 to ease timing closure g_rd_latency => g_rd_latency -- 1 or 2, choose 2 to ease timing closure
......
libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+ 5
− 7
View file @ 6d969ed3
...@@ -54,12 +54,11 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS ...@@ -54,12 +54,11 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
CONSTANT c_sim_nof_blocks : NATURAL := c_nof_block_per_sync * c_nof_input_sync; CONSTANT c_sim_nof_blocks : NATURAL := c_nof_block_per_sync * c_nof_input_sync;
CONSTANT c_nof_streams : NATURAL := 2; CONSTANT c_nof_streams : NATURAL := 2;
CONSTANT c_bsn_latency_max : NATURAL := 2; CONSTANT c_bsn_latency_max : POSITIVE := 2;
CONSTANT c_bsn_latency_use_node_index : BOOLEAN := FALSE; CONSTANT c_nof_aligners_max : NATURAL := 1;
CONSTANT c_buffer_nof_blocks : NATURAL := ceil_pow2(1 + c_bsn_latency_max);
CONSTANT c_bsn_w : NATURAL := c_dp_stream_bsn_w; CONSTANT c_bsn_w : NATURAL := c_dp_stream_bsn_w;
CONSTANT c_data_w : NATURAL := 16; CONSTANT c_data_w : NATURAL := 16;
CONSTANT c_filler_value : INTEGER := 0; CONSTANT c_replacement_value : INTEGER := 0;
CONSTANT c_nof_clk_per_sync : NATURAL := 200*10**6; CONSTANT c_nof_clk_per_sync : NATURAL := 200*10**6;
CONSTANT c_nof_input_bsn_monitors : NATURAL := 0; CONSTANT c_nof_input_bsn_monitors : NATURAL := 0;
CONSTANT c_use_bsn_output_monitor : BOOLEAN := FALSE; CONSTANT c_use_bsn_output_monitor : BOOLEAN := FALSE;
...@@ -153,12 +152,11 @@ BEGIN ...@@ -153,12 +152,11 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
g_nof_streams => c_nof_streams, g_nof_streams => c_nof_streams,
g_bsn_latency_max => c_bsn_latency_max, g_bsn_latency_max => c_bsn_latency_max,
g_bsn_latency_use_node_index => c_bsn_latency_use_node_index, g_nof_aligners_max => c_nof_aligners_max,
g_block_size => c_block_size, g_block_size => c_block_size,
g_buffer_nof_blocks => c_buffer_nof_blocks,
g_bsn_w => c_bsn_w, g_bsn_w => c_bsn_w,
g_data_w => c_data_w, g_data_w => c_data_w,
g_filler_value => c_filler_value, g_replacement_value => c_replacement_value,
g_nof_clk_per_sync => c_nof_clk_per_sync, g_nof_clk_per_sync => c_nof_clk_per_sync,
g_nof_input_bsn_monitors => c_nof_input_bsn_monitors, g_nof_input_bsn_monitors => c_nof_input_bsn_monitors,
g_use_bsn_output_monitor => c_use_bsn_output_monitor g_use_bsn_output_monitor => c_use_bsn_output_monitor
......
libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+ 6
− 6
View file @ 6d969ed3
...@@ -37,7 +37,7 @@ ARCHITECTURE tb OF tb_tb_dp_bsn_align_v2 IS ...@@ -37,7 +37,7 @@ ARCHITECTURE tb OF tb_tb_dp_bsn_align_v2 IS
CONSTANT c_block_size : NATURAL := 11; CONSTANT c_block_size : NATURAL := 11;
CONSTANT c_diff_delay : NATURAL := 20; CONSTANT c_diff_delay : NATURAL := 20;
CONSTANT c_diff_bsn : NATURAL := 3; -- g_diff_bsn = g_bsn_latency can just be aligned CONSTANT c_diff_bsn : NATURAL := 3; -- g_diff_bsn = g_bsn_latency can just be aligned
CONSTANT c_bsn_latency_max : NATURAL := 1; CONSTANT c_bsn_latency_max : POSITIVE := 1;
CONSTANT c_nof_repeat : NATURAL := 100; -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli CONSTANT c_nof_repeat : NATURAL := 100; -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end' SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
...@@ -46,11 +46,11 @@ BEGIN ...@@ -46,11 +46,11 @@ BEGIN
-- -- DUT -- -- DUT
-- g_nof_streams : NATURAL := 2; -- number of input and output streams -- g_nof_streams : NATURAL := 2; -- number of input and output streams
-- g_bsn_latency_max : NATURAL := 1; -- Maximum travel latency of a remote block in number of block periods T_blk -- g_bsn_latency_max : NATURAL := 1; -- Maximum travel latency of a remote block in number of block periods T_blk
-- g_bsn_latency_use_node_index : BOOLEAN := FALSE; -- FALSE for align at end node, TRUE for align at every intermediate node -- g_nof_aligners_max : NATURAL := 1; -- 1 when only align at last node, > 1 when align at every intermediate node
-- g_block_size : NATURAL := 11; -- > 1, g_block_size=1 is not supported -- g_block_size : NATURAL := 11; -- > 1, g_block_size=1 is not supported
-- g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN -- g_bsn_w : NATURAL := c_dp_stream_bsn_w; -- number of bits in sosi BSN
-- g_data_w : NATURAL := 16; -- number of bits in sosi data -- g_data_w : NATURAL := 16; -- number of bits in sosi data
-- g_filler_value : INTEGER := 0; -- output sosi data value for missing input blocks -- c_replacement_value : INTEGER := 0; -- output sosi data replacement value for missing input blocks
-- g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP -- g_use_mm_output : BOOLEAN := FALSE; -- output via MM or via streaming DP
-- g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure -- g_pipeline_input : NATURAL := 1; -- >= 0, choose 0 for wires, choose 1 to ease timing closure
-- g_rd_latency : NATURAL := 2; -- 1 or 2, choose 2 to ease timing closure -- g_rd_latency : NATURAL := 2; -- 1 or 2, choose 2 to ease timing closure
...@@ -60,7 +60,7 @@ BEGIN ...@@ -60,7 +60,7 @@ BEGIN
-- g_diff_bsn : NATURAL := 0; -- g_diff_bsn = g_bsn_latency_max can just be aligned -- g_diff_bsn : NATURAL := 0; -- g_diff_bsn = g_bsn_latency_max can just be aligned
-- g_nof_repeat : NATURAL := 100 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli -- g_nof_repeat : NATURAL := 100 -- for constant active stream control using 1 is sufficient, use > 1 to verify longer with random stimuli
u_mm_output : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, FALSE, 11, 32, 16, 0, TRUE, 0, 1, 0, 9, c_nof_repeat); u_mm_output : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, 11, 32, 16, 0, TRUE, 0, 1, 0, 9, c_nof_repeat);
u_dp_output : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, FALSE, 11, 32, 16, 0, FALSE, 0, 1, 0, 9, c_nof_repeat); u_dp_output : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, c_bsn_latency_max, 1, 11, 32, 16, 0, FALSE, 0, 1, 0, 9, c_nof_repeat);
END tb; END tb;
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