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Commit 6d95dfdc authored by Pepping's avatar Pepping
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Updated constraints after DDR3 phy with settings of Jonathan.

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boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl
+ 35
− 35
View file @ 6d95dfdc
......@@ -478,40 +478,40 @@ set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[5] -tag __uphy_4g_800_master_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[6] -tag __uphy_4g_800_master_p0
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[7] -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[5]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[6]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_n" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[5]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[6]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[7]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst" -tag __uphy_4g_800_master_p0
set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to "u_ddr3_T|u_seq_ddr3|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|pll1" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[5]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[6]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_n" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[5]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[6]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[7]" -tag __uphy_4g_800_master_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst" -tag __uphy_4g_800_master_p0
set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to "u_ddr3_T|u_ddr3|\\gen_uphy_4g_800_master:u_uphy_4g_800_master|uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|pll1" -tag __uphy_4g_800_master_p0
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name UNIPHY_TEMP_VER_CODE 1979019194
\ No newline at end of file
set_global_assignment -name UNIPHY_TEMP_VER_CODE 1231196504
\ No newline at end of file
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