Added MM to DP component, to verify via out_sosi_arr.

libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd

@@ -42,7 +42,7 @@ ENTITY tb_dp_bsn_align_v2 IS
     g_bsn_latency_use_node_index : BOOLEAN := FALSE;  -- FALSE for align at end node, TRUE for align at every intermediate node
     g_block_size                 : NATURAL := 17;     -- > 1, g_block_size=1 is not supported
     g_bsn_w                      : NATURAL := c_dp_stream_bsn_w;  -- number of bits in sosi BSN
-    g_data_w                     : NATURAL;           -- number of bits in sosi data
+    g_data_w                     : NATURAL := 16;     -- number of bits in sosi data
     g_filler_value               : INTEGER := 0;      -- output sosi data value for missing input blocks
 
     -- TB
@@ -107,9 +107,12 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS
   SIGNAL in_err            : t_err_arr;
   SIGNAL in_channel        : t_channel_arr;
   
+  SIGNAL mm_copi_arr       : t_mem_copi_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL mm_copi           : t_mem_copi;   -- read access to output block, all output streams share same mm_copi
   SIGNAL mm_cipo_arr       : t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL mm_sosi           : t_dp_sosi;   -- streaming information that signals that an output block can be read
+  SIGNAL mm_done_arr       : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+  SIGNAL mm_done           : STD_LOGIC;
 
   SIGNAL out_siso_arr      : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
   SIGNAL out_sosi_arr      : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
@@ -422,4 +425,34 @@ BEGIN
     mm_sosi        => mm_sosi
   );
 
+
+  ------------------------------------------------------------------------------
+  -- MM to streaming DP
+  ------------------------------------------------------------------------------
+
+  gen_mm_to_dp : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    u_mm_to_dp: ENTITY work.dp_block_from_mm
+    GENERIC MAP (
+      g_data_size          => 1,
+      g_step_size          => 1,
+      g_nof_data           => g_block_size,
+      g_data_w             => g_data_w,
+      g_reverse_word_order => FALSE
+    )
+    PORT MAP (
+      rst           => rst,
+      clk           => clk,
+      start_pulse   => mm_sosi.sop,
+      start_address => 0,
+      mm_done       => mm_done_arr(I),
+      mm_mosi       => mm_copi_arr(I),
+      mm_miso       => mm_cipo_arr(I),
+      out_sosi      => out_sosi_arr(I),
+      out_siso      => c_dp_siso_rdy
+    );
+  END GENERATE;
+
+  mm_copi <= mm_copi_arr(0);
+  mm_done <= mm_done_arr(0);
+  
 END tb;