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Commit 6b512015 authored by Eric Kooistra's avatar Eric Kooistra
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Use common_pulser_us_ms_s instead of unb2_board_pulser.

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......@@ -15,7 +15,6 @@ synth_files =
src/vhdl/unb2_board_clk200_pll.vhd
src/vhdl/unb2_board_clk25_pll.vhd
src/vhdl/unb2_board_clk125_pll.vhd
src/vhdl/unb2_board_pulser.vhd
src/vhdl/unb2_board_wdi_extend.vhd
src/vhdl/unb2_board_node_ctrl.vhd
src/vhdl/unb2_board_sens_ctrl.vhd
......
......@@ -100,7 +100,7 @@ BEGIN
out_rst => st_rst
);
u_unb2_board_pulser : ENTITY work.unb2_board_pulser
u_common_pulser_us_ms_s : ENTITY common_lib.common_pulser_us_ms_s
GENERIC MAP (
g_pulse_us => g_pulse_us,
g_pulse_ms => g_pulse_ms,
......
-------------------------------------------------------------------------------
--
-- Copyright (C) 2010
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
-- Purpose: Provide timing pulses for interval 1 us, 1 ms and 1 s
ENTITY unb2_board_pulser IS
GENERIC (
g_pulse_us : NATURAL := 125/(10**6); -- nof clk cycles to get us period
g_pulse_ms : NATURAL := 1000; -- nof pulse_us pulses to get ms period
g_pulse_s : NATURAL := 1000 -- nof pulse_ms pulses to get s period
);
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
sync : IN STD_LOGIC := '0';
pulse_us : OUT STD_LOGIC; -- pulses after every g_pulse_us clock cycles
pulse_ms : OUT STD_LOGIC; -- pulses after every g_pulse_us*g_pulse_ms clock cycles
pulse_s : OUT STD_LOGIC -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
);
END unb2_board_pulser;
ARCHITECTURE str OF unb2_board_pulser IS
SIGNAL pulse_us_pp : STD_LOGIC; -- register to align with pulse_ms
SIGNAL pulse_us_p : STD_LOGIC; -- register to align with pulse_s
SIGNAL pulse_us_reg : STD_LOGIC; -- output register
SIGNAL i_pulse_us : STD_LOGIC;
SIGNAL pulse_ms_p : STD_LOGIC; -- register to align with pulse_s
SIGNAL pulse_ms_reg : STD_LOGIC; -- output register
SIGNAL i_pulse_ms : STD_LOGIC;
SIGNAL pulse_s_reg : STD_LOGIC; -- output register
SIGNAL i_pulse_s : STD_LOGIC;
BEGIN
pulse_us <= i_pulse_us;
pulse_ms <= i_pulse_ms;
pulse_s <= i_pulse_s;
p_clk : PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
pulse_us_p <= pulse_us_pp;
pulse_us_reg <= pulse_us_p;
pulse_ms_reg <= pulse_ms_p;
i_pulse_us <= pulse_us_reg;
i_pulse_ms <= pulse_ms_reg;
i_pulse_s <= pulse_s_reg;
END IF;
END PROCESS;
u_common_pulser_us : ENTITY common_lib.common_pulser
GENERIC MAP (
g_pulse_period => g_pulse_us
)
PORT MAP (
rst => rst,
clk => clk,
clken => '1',
pulse_en => '1',
pulse_clr => sync,
pulse_out => pulse_us_pp
);
u_common_pulser_ms : ENTITY common_lib.common_pulser
GENERIC MAP (
g_pulse_period => g_pulse_ms
)
PORT MAP (
rst => rst,
clk => clk,
clken => '1',
pulse_en => pulse_us_pp,
pulse_clr => sync,
pulse_out => pulse_ms_p
);
u_common_pulser_s : ENTITY common_lib.common_pulser
GENERIC MAP (
g_pulse_period => g_pulse_s
)
PORT MAP (
rst => rst,
clk => clk,
clken => '1',
pulse_en => pulse_ms_p,
pulse_clr => sync,
pulse_out => pulse_s_reg
);
END str;
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