Added tb_node_unb1_bn_capture.vhd to regression tests.

boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg

@@ -15,6 +15,9 @@ test_bench_files =
     tb/vhdl/tb_node_unb1_bn_capture.vhd
     #tb/vhdl/tb_unb1_bn_capture.vhd
 
+regression_test_vhdl = 
+    tb/vhdl/tb_unb1_bn_capture_input.vhd
+    tb/vhdl/tb_node_unb1_bn_capture.vhd
 
 [modelsim_project_file]
 modelsim_copy_files = $RADIOHDL/libraries/io/i2c/tb/data data   

boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd

@@ -22,14 +22,22 @@
 -- Purpose: Test bench for node_bn_capture
 --
 -- Features:
+-- . Perform I2C read access to ADU.
 -- . Schedule WG start at a BSN
 -- . Optionally add stimuli for DDR3 storage in p_reg_ddr3_stimuli and
 --   enable the ddr3_I and or ddr3_II in g_use_phy.
 --
 -- Usage:
--- . > do wave_node_bn_capture.do
--- . > run 50 us
--- . Observe in Wave Window that the WG indeed do start
+-- . > as 10
+-- . > run -a
+-- . Observe in Wave Window that the WG indeed do start. Therefore manually
+--   view sp_sosi_arr at the sample rate using the 4 SP scope_sosi_arr().data
+--   in node_unb1_bn_capture/unb1_bn_capture_input/aduh_quad_scope/
+--   dp_wideband_sp_arr_scope and viewing these integer data fields as
+--   Radix=decimal and Format=analogue.
+-- . The self test only verifies the exp_result_data for the ADU I2C access.
+--   The tb_end depends on reg stimuli done and I2C stimuli done so that
+--   proves that the tb has run.
 
 
 LIBRARY IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, aduh_lib, i2c_lib;
@@ -127,6 +135,11 @@ ARCHITECTURE tb OF tb_node_unb1_bn_capture IS
   SIGNAL ADC_CD_SCL                : STD_LOGIC;
   SIGNAL ADC_CD_SDA                : STD_LOGIC;
     
+  -- Test bench
+  SIGNAL tb_end                    : STD_LOGIC := '0';
+  SIGNAL reg_input_stimuli_done    : STD_LOGIC := '0';
+  SIGNAL i2c_adu_stimuli_done      : STD_LOGIC := '0';
+  
   -- DUT
   SIGNAL mm_clk                    : STD_LOGIC := '0';
   SIGNAL mm_locked                 : STD_LOGIC := '0';
@@ -186,7 +199,9 @@ ARCHITECTURE tb OF tb_node_unb1_bn_capture IS
   -- Commander results [0,1] for ADU-[AB,CD]
   SIGNAL cmdr_protocol_status      : t_natural_arr(0 TO c_ai.nof_adu-1);
   SIGNAL cmdr_result_data          : t_natural_arr(0 TO c_ai.nof_adu-1);
+  SIGNAL exp_result_data           : t_natural_arr(0 TO c_ai.nof_adu-1) := (0, 60);  -- expected temp 60 degrees in adu_half
   SIGNAL cmdr_result_error_cnt     : t_natural_arr(0 TO c_ai.nof_adu-1);
+  SIGNAL exp_result_error_cnt      : t_natural_arr(0 TO c_ai.nof_adu-1) := (0, 0);
  
   -- MM bsn schedule SP
   SIGNAL reg_bsn_scheduler_sp_on_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -200,12 +215,14 @@ BEGIN
   -- System setup
   ----------------------------------------------------------------------------
   
-  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- 1GbE XO clock (25 MHz)
+  tb_end <= '0', reg_input_stimuli_done AND i2c_adu_stimuli_done AFTER c_mm_clk_period*100;
+  
+  eth_clk <= NOT eth_clk OR tb_end AFTER c_eth_clk_period/2;  -- 1GbE XO clock (25 MHz)
   
-  mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;  -- MM clock (50 MHz)
+  mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;  -- MM clock (50 MHz)
   mm_locked <= '0', '1' AFTER c_mm_clk_period*7;
   
-  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  ext_clk <= NOT ext_clk OR tb_end AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
   
   INTA <= 'H';  -- pull up
   INTB <= 'H';  -- pull up
@@ -289,12 +306,13 @@ BEGIN
       
       -- Write scheduler BSN to trigger start of WG at next block
       v_bsn := TO_UINT(current_bsn_wg) + 2;
-      proc_mem_mm_bus_wr(1,     0, mm_clk, reg_bsn_scheduler_wg_mosi);
-      proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi);   -- assume v_bsn < 2**31-1
+      proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi);   -- first write low then high part
+      proc_mem_mm_bus_wr(1,     0, mm_clk, reg_bsn_scheduler_wg_mosi);   -- assume v_bsn < 2**31-1
       
       -- Continue forever with WG data
     END IF;
-        
+    proc_common_wait_some_cycles(mm_clk, 1000);
+    reg_input_stimuli_done <= '1';
     WAIT;
   END PROCESS;
   
@@ -308,7 +326,7 @@ BEGIN
     CONSTANT c_result_error_cnt_wi  : NATURAL := 3*c_i2c_cmdr_aduh_protocol_commander.nof_protocols + 1;
     CONSTANT c_result_data_wi       : NATURAL := 3*c_i2c_cmdr_aduh_protocol_commander.nof_protocols + 2;
   
-    CONSTANT c_A : NATURAL RANGE 0 to c_ai.nof_adu-1 := 1;
+    CONSTANT c_A : NATURAL RANGE 0 to c_ai.nof_adu-1 := 1;  -- only try ADUH index (1) = ADU-CD
     CONSTANT c_P : NATURAL := 0;  -- 0 = c_i2c_adu_max1617_protocol_list_read_temp --> expected temp 60 degrees in adu_half
   BEGIN
     reg_commander_mosi_arr <= (OTHERS=>c_mem_mosi_rst);
@@ -357,7 +375,10 @@ BEGIN
       cmdr_protocol_status(c_A) <= TO_UINT(reg_commander_miso_arr(c_A).rddata);
       proc_common_wait_some_cycles(mm_clk, 1);
     END LOOP;
-      
+    proc_common_wait_some_cycles(mm_clk, 100);
+    i2c_adu_stimuli_done <= '1';
+    ASSERT cmdr_result_data      = exp_result_data      REPORT "Unexpected ADU temperature read via I2C" SEVERITY ERROR;
+    ASSERT cmdr_result_error_cnt = exp_result_error_cnt REPORT "Unexpected ADU I2C access error count > 0" SEVERITY ERROR;
     WAIT;
   END PROCESS;
      
@@ -504,7 +525,7 @@ BEGIN
   -----------------------------------------------------------------------------
   
   -- Same sample clock for all ADC
-  SCLK <= NOT SCLK AFTER c_sample_period/2;
+  SCLK <= NOT SCLK OR tb_end AFTER c_sample_period/2;
   
   -- Same analogue reference signal for all ADC, use incrementing data to ease the verification
   ANA_DAT <= INCR_UVEC(ANA_DAT, 1) WHEN rising_edge(SCLK);
@@ -514,9 +535,6 @@ BEGIN
   ANA_D   <= INCR_UVEC(ANA_DAT, 3*c_ana_diff);
   ANA_OVR <= NOT ANA_OVR WHEN rising_edge(SCLK);  -- simple overflow model used for both ADC
   
-  -- Same sample clock for all ADC
-  SCLK <= NOT SCLK AFTER c_sample_period/2;
-
   -- National ADC
   u_adc_AB : ENTITY aduh_lib.adu_half
   PORT MAP (

boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd

@@ -306,7 +306,7 @@ BEGIN
     
     -- Write BSN scheduler to trigger start of WG at specific block
     v_bsn := c_bsn_schedule_wg_on;
-    proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi);
+    proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi);   -- first write low then high part
     proc_mem_mm_bus_wr(1,     0, mm_clk, reg_bsn_scheduler_wg_mosi);   -- assume v_bsn < 2**31-1
     
     -- Read aduh locked status for AB, CD to set initial stable reference moment