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RTSD
HDL
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6a463d90
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6a463d90
authored
Jul 10, 2015
by
Eric Kooistra
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Updated README for usage.
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boards/uniboard1/designs/unb1_ddr3/doc/README
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To generate the IP files; use the Megawizard.
Quick steps to compile and use design [unb1_ddr3] in RadionHDL
$UNB/Firmware/modules/ddr3/src/ip/megawizard
--------------------------------------------------------------
run the commands:
Start with the Oneclick Commands:
python $RADIOHDL/tools/oneclick/base/modelsim_config.py
python $RADIOHDL/tools/oneclick/base/quartus_config.py
cd $UNB/Firmware/modules/ddr3/src/ip/megawizard
Generate MMM for SOPC:
unb_mgw
ddr3
run_sopc unb1 unb1_
ddr3
-> From here either continue to Modelsim (simulation) or Quartus (synthesis)
Simulation
----------
Modelsim instructions:
# in bash do:
rm $UNB/Software/python/sim/* # (optional)
run_modelsim unb1
# in Modelsim do:
lp unb1_ddr3
mk all
# now double click on testbench file tb_unb1_ddr3
as 10
run 500us
# while the simulation runs... in another bash session do:
cd unb1_ddr3/tb/python
python tc_unb1_ddr3_seq.py --sim --unb 0 --fn 3 --rep 3 -v 5 -n 0
# note --fn 3 must match the node setting in the tb_unb1_ddr3.
# the test can run again:
python tc_unb1_ddr3_seq.py --sim --unb 0 --fn 3 --rep 3 -v 3 -n 0
# to end simulation in Modelsim do:
quit -sim
Quartus instructions:
# GUI:
run_quartus unb1 &
# Open project unb1_ddr3.qpf and Start compilation
or
# Command line:
run_qcomp unb1 unb1_ddr3
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boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
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Quick steps to compile and use design [unb1_ddr3_reorder] in RadionHDL
--------------------------------------------------------------
Start with the Oneclick Commands:
python $RADIOHDL/tools/oneclick/base/modelsim_config.py
python $RADIOHDL/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC:
run_sopc unb1 unb1_ddr3_reorder
-> From here either continue to Modelsim (simulation) or Quartus (synthesis)
Simulation
----------
Modelsim instructions:
# in bash do:
rm $UNB/Software/python/sim/* # (optional)
run_modelsim unb1
# in Modelsim do:
lp unb1_ddr3_reorder
mk all
# now double click on testbench file tb_unb1_ddr3_reorder
as 10
run 500us
# while the simulation runs... in another bash session do:
cd unb1_ddr3_reorder/tb/python
python tc_unb1_ddr3_reorder_seq.py --sim --unb 0 --bn 3 --rep 3 -v 5 -n 0
# note --bn 3 must match the node setting in the tb_unb1_ddr3_reorder.
# to run the test again use --read or --rerun:
python tc_unb1_ddr3_reorder_seq.py --sim --unb 0 --bn 3 --rep 1 -v 3 -n 0 --read
python tc_unb1_ddr3_reorder_seq.py --sim --unb 0 --bn 3 --rep 1 -v 3 -n 0 --rerun
# to end simulation in Modelsim do:
quit -sim
Quartus instructions:
# GUI:
run_quartus unb1 &
# Open project unb1_ddr3_reorder.qpf and Start compilation
or
# Command line:
run_qcomp unb1 unb1_ddr3_reorder
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