-updat constants and added quartis dir

applications/unb1_fn_bf/hdllib.cfg

@@ -9,12 +9,13 @@ build_dir_synth = $HDL_BUILD_DIR
 synth_top_level_entity =
 
 synth_files =   
-    $UNB/Firmware/designs/fn_bf/src/vhdl/mmm_fn_bf.vhd
-    $UNB/Firmware/designs/fn_bf/src/vhdl/node_fn_bf.vhd
-    src/vhdl/fb_bf.vhd
+    $HDL_BUILD_DIR/quartus/unb1_fn_bf_sopc/sopc_unb1_fn_bf.vhd
+    src/vhdl/unb1_mmm_fn_bf.vhd
+    src/vhdl/unb1_node_fn_bf.vhd
+    src/vhdl/unb1_fn_bf.vhd
     
 test_bench_files = 
-    tb/vhdl/tb_apertif_unb1_correlator.vhd
+    $UNB/Firmware/designs/fn_bf/tb/vhdl/tb_fn_bf.vhd
 
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf

applications/unb1_fn_bf/src/vhdl/unb1_mmm_fn_bf.vhd

@@ -19,20 +19,25 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb_common_lib, mm_lib, tse_lib, bf_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, bf_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE unb_common_lib.unb_common_pkg.ALL;
-USE unb_common_lib.unb_peripherals_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
 USE mm_lib.mm_file_pkg.ALL;
 USE mm_lib.mm_file_unb_pkg.ALL;
 USE common_lib.tb_common_mem_pkg.ALL;
-USE tse_lib.tse_pkg.ALL;
-USE tse_lib.tb_tse_pkg.ALL;
-USE tse_lib.eth_pkg.ALL;
-USE tse_lib.eth_layers_pkg.ALL;
+--USE tse_lib.tse_pkg.ALL;
+--USE tse_lib.tb_tse_pkg.ALL;
+USE eth_lib.eth_pkg.ALL; 
+USE technology_lib.technology_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+--USE tse_lib.eth_layers_pkg.ALL;
 USE bf_lib.bf_pkg.ALL;
 
 ENTITY mmm_fn_bf IS
@@ -126,8 +131,8 @@ ARCHITECTURE str OF mmm_fn_bf IS
   CONSTANT c_reg_st_sst_bf_addr_w   : NATURAL := ceil_log2(c_bf_max_nof_bf_units)*2;  -- 2 bits reserved for single reg_st_sst.  
   CONSTANT c_ram_ss_ss_wide_addr_w  : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_weights*g_bf.nof_signal_paths);
   -- BF offload                                                                                                       
-  CONSTANT c_hdr_nof_words          : NATURAL := c_eth_total_header_nof_words;
-  CONSTANT c_dp_ram_mm_nof_words    : NATURAL := c_hdr_nof_words * (c_tse_data_w/c_word_w);
+  CONSTANT c_hdr_nof_words          : NATURAL := c_network_total_header_32b_nof_words;
+  CONSTANT c_dp_ram_mm_nof_words    : NATURAL := c_hdr_nof_words * (c_eth_data_w/c_word_w);
   CONSTANT c_dp_ram_mm_adr_w        : NATURAL := ceil_log2(c_dp_ram_mm_nof_words);
   
     -- Simulation
@@ -158,10 +163,9 @@ ARCHITECTURE str OF mmm_fn_bf IS
   );
   END COMPONENT;               
 
-  CONSTANT c_dut_src_mac       : STD_LOGIC_VECTOR(c_eth_mac_slv'RANGE) := X"002286080001";
+  CONSTANT c_dut_src_mac           : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"002286080001";
   SIGNAL eth_psc_access            : STD_LOGIC;
                                    
-  CONSTANT c_dut_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
                                    
   SIGNAL reg_ppsh_mosi             : t_mem_mosi := c_mem_mosi_rst;
   SIGNAL reg_ppsh_miso             : t_mem_miso := c_mem_miso_rst;
@@ -172,9 +176,13 @@ ARCHITECTURE str OF mmm_fn_bf IS
   SIGNAL eth1g_reg_proc_mosi       : t_mem_mosi;
   SIGNAL eth1g_reg_proc_miso       : t_mem_miso;
 
-  SIGNAL mm_bus_switch         : STD_LOGIC;
+  CONSTANT c_sim_eth_src_mac       : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
+  CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
 
+  SIGNAL sim_eth_mm_bus_switch     : STD_LOGIC;
+  SIGNAL sim_eth_psc_access        : STD_LOGIC;
                                    
+  SIGNAL sim_eth1g_reg_mosi        : t_mem_mosi;
   
 BEGIN
   
@@ -249,30 +257,59 @@ BEGIN
     ----------------------------------------------------------------------------
     p_eth_setup : PROCESS
     BEGIN
-      mm_bus_switch <= '1';
+      sim_eth_mm_bus_switch <= '1';
 
       eth1g_tse_mosi.wr <= '0';
       eth1g_tse_mosi.rd <= '0';
       WAIT FOR 400 ns;
       WAIT UNTIL rising_edge(i_mm_clk);
-      proc_tse_setup(FALSE, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tse_tx_ready_latency, c_dut_src_mac, eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+      proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
 
       -- Enable RX
-      proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi);  -- control rx en
-      mm_bus_switch <= '0';
+      proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);  -- control rx en
+      sim_eth_mm_bus_switch <= '0';
 
       WAIT;
     END PROCESS;
 
-    p_switch : PROCESS(mm_bus_switch, eth1g_reg_proc_mosi, i_eth1g_reg_mosi)
+    p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
     BEGIN
-      IF mm_bus_switch = '1' THEN 
-          eth1g_reg_mosi <= eth1g_reg_proc_mosi;
+      IF sim_eth_mm_bus_switch = '1' THEN
+          eth1g_reg_mosi <= sim_eth1g_reg_mosi;
         ELSE
           eth1g_reg_mosi <= i_eth1g_reg_mosi;
         END IF;
     END PROCESS;
 
+    ----------------------------------------------------------------------------
+    -- 1GbE setup sequence normally performed by unb_os@NIOS
+    ----------------------------------------------------------------------------
+    --p_eth_setup : PROCESS
+    --BEGIN
+    --  mm_bus_switch <= '1';
+    --
+    --  eth1g_tse_mosi.wr <= '0';
+    --  eth1g_tse_mosi.rd <= '0';
+    --  WAIT FOR 400 ns;
+    --  WAIT UNTIL rising_edge(i_mm_clk);
+    --  proc_tse_setup(FALSE, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tse_tx_ready_latency, c_dut_src_mac, eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+    --
+    --  -- Enable RX
+    --  proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi);  -- control rx en
+    --  mm_bus_switch <= '0';
+    --
+    --  WAIT;
+    --END PROCESS;
+    --
+    --p_switch : PROCESS(mm_bus_switch, eth1g_reg_proc_mosi, i_eth1g_reg_mosi)
+    --BEGIN
+    --  IF mm_bus_switch = '1' THEN 
+    --      eth1g_reg_mosi <= eth1g_reg_proc_mosi;
+    --    ELSE
+    --      eth1g_reg_mosi <= i_eth1g_reg_mosi;
+    --    END IF;
+    --END PROCESS;
+
     ----------------------------------------------------------------------------
     -- Procedure that polls a sim control file that can be used to e.g. get
     -- the simulation time in ns
@@ -306,26 +343,26 @@ BEGIN
       -- the_avs_eth_0
       coe_clk_export_from_the_avs_eth_0             => OPEN,
       coe_reset_export_from_the_avs_eth_0           => eth1g_mm_rst,
-      coe_tse_address_export_from_the_avs_eth_0     => eth1g_tse_mosi.address(c_tse_byte_addr_w-1 DOWNTO 0),
+      coe_tse_address_export_from_the_avs_eth_0     => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
       coe_tse_write_export_from_the_avs_eth_0       => eth1g_tse_mosi.wr,
       coe_tse_writedata_export_from_the_avs_eth_0   => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
       coe_tse_read_export_from_the_avs_eth_0        => eth1g_tse_mosi.rd,
       coe_tse_readdata_export_to_the_avs_eth_0      => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_tse_waitrequest_export_to_the_avs_eth_0   => eth1g_tse_miso.waitrequest,
-      coe_reg_address_export_from_the_avs_eth_0     => eth1g_reg_mosi.address(c_eth_reg_addr_w-1 DOWNTO 0),
+      coe_reg_address_export_from_the_avs_eth_0     => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
       coe_reg_write_export_from_the_avs_eth_0       => eth1g_reg_mosi.wr,
       coe_reg_writedata_export_from_the_avs_eth_0   => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
       coe_reg_read_export_from_the_avs_eth_0        => eth1g_reg_mosi.rd,
       coe_reg_readdata_export_to_the_avs_eth_0      => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_irq_export_to_the_avs_eth_0               => eth1g_reg_interrupt,
-      coe_ram_address_export_from_the_avs_eth_0     => eth1g_ram_mosi.address(c_eth_ram_addr_w-1 DOWNTO 0),
+      coe_ram_address_export_from_the_avs_eth_0     => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
       coe_ram_write_export_from_the_avs_eth_0       => eth1g_ram_mosi.wr,
       coe_ram_writedata_export_from_the_avs_eth_0   => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
       coe_ram_read_export_from_the_avs_eth_0        => eth1g_ram_mosi.rd,
       coe_ram_readdata_export_to_the_avs_eth_0      => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
   
       -- the_reg_unb_sens
-      coe_address_export_from_the_reg_unb_sens       => reg_unb_sens_mosi.address(c_unb_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+      coe_address_export_from_the_reg_unb_sens   => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
       coe_clk_export_from_the_reg_unb_sens       => OPEN,                                            
       coe_read_export_from_the_reg_unb_sens      => reg_unb_sens_mosi.rd,                                  
       coe_readdata_export_to_the_reg_unb_sens    => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),         
@@ -393,7 +430,7 @@ BEGIN
       -- the_pio_pps
       coe_clk_export_from_the_pio_pps               => OPEN,
       coe_reset_export_from_the_pio_pps             => OPEN,
-      coe_address_export_from_the_pio_pps           => reg_ppsh_mosi.address(c_unb_mm_reg_default.reg_ppsh_adr_w-1),  -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+      coe_address_export_from_the_pio_pps           => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1),  -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
       coe_read_export_from_the_pio_pps              => reg_ppsh_mosi.rd,
       coe_readdata_export_to_the_pio_pps            => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_write_export_from_the_pio_pps             => reg_ppsh_mosi.wr,
@@ -402,7 +439,7 @@ BEGIN
       -- the_pio_system_info: actually a avs_common_mm instance
       coe_clk_export_from_the_pio_system_info         => OPEN,
       coe_reset_export_from_the_pio_system_info       => OPEN,
-      coe_address_export_from_the_pio_system_info     => reg_unb_system_info_mosi.address(c_unb_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), 
+      coe_address_export_from_the_pio_system_info     => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), 
       coe_read_export_from_the_pio_system_info        => reg_unb_system_info_mosi.rd,
       coe_readdata_export_to_the_pio_system_info      => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_write_export_from_the_pio_system_info       => reg_unb_system_info_mosi.wr,
@@ -411,7 +448,7 @@ BEGIN
       -- the_rom_system_info
       coe_clk_export_from_the_rom_system_info         => OPEN,
       coe_reset_export_from_the_rom_system_info       => OPEN,
-      coe_address_export_from_the_rom_system_info     => rom_unb_system_info_mosi.address(c_unb_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
+      coe_address_export_from_the_rom_system_info     => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
       coe_read_export_from_the_rom_system_info        => rom_unb_system_info_mosi.rd,
       coe_readdata_export_to_the_rom_system_info      => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_write_export_from_the_rom_system_info       => rom_unb_system_info_mosi.wr,