added GENERIC g_epcs_addr_w

libraries/io/epcs/hdllib.cfg

@@ -7,7 +7,7 @@ build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
-    $UNB/Firmware/modules/epcs/src/vhdl/epcs_reg.vhd
+    src/vhdl/epcs_reg.vhd
     src/vhdl/mms_epcs.vhd
 
 test_bench_files = 

libraries/io/epcs/src/vhdl/epcs_reg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+--  RO  read only  (no VHDL present to access HW in write mode)
+--  WO  write only (no VHDL present to access HW in read mode)
+--  WE  write event (=WO)
+--  WR  write control, read control
+--  RW  read status, write control  
+--  RC  read, clear on read
+--  FR  FIFO read
+--  FW  FIFO write
+--
+--  wi  Bits    R/W Name              Default  Description             |REG_EPCS|                      
+--  =============================================================================
+--  0   [23..0] WO  addr              0x0      Address to write to/read from
+--  1   [0]     WO  rden              0x0      Read enable
+--  2   [0]     WE  read              0x0      Read 
+--  3   [0]     WE  write             0x0      Write 
+--  4   [0]     WO  sector_erase      0x0      Sector erase
+--  5   [0]     RO  busy              0x0      Busy
+--  =============================================================================
+--
+--  Refer to the user guide of Altera's ALTASMI_PARALLEL megafunction for more
+--  information.
+   
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY epcs_reg IS
+  GENERIC (
+    g_epcs_addr_w : NATURAL := 24
+  );
+  PORT (
+    -- Clocks and reset
+    mm_rst                   : IN  STD_LOGIC;    
+    mm_clk                   : IN  STD_LOGIC;
+   
+    epcs_rst                 : IN  STD_LOGIC;    
+    epcs_clk                 : IN  STD_LOGIC;
+ 
+    -- Memory Mapped Slave   
+    sla_in                   : IN  t_mem_mosi; 
+    sla_out                  : OUT t_mem_miso;
+
+    epcs_in_addr             : OUT STD_LOGIC_VECTOR(g_epcs_addr_w-1 DOWNTO 0);
+    epcs_in_read_evt         : OUT STD_LOGIC;
+    epcs_in_rden             : OUT STD_LOGIC;
+    epcs_in_write_evt        : OUT STD_LOGIC;
+    epcs_in_sector_erase_evt : OUT STD_LOGIC;
+
+    epcs_out_busy            : IN STD_LOGIC
+
+    );
+END epcs_reg;
+
+
+ARCHITECTURE rtl OF epcs_reg IS
+
+  CONSTANT c_mm_reg        : t_c_mem := (latency  => 1,
+                                         adr_w    => ceil_log2(6),
+                                         dat_w    => c_word_w,       -- Use MM bus data width = c_word_w = 32 for all MM registers
+                                         nof_dat  => 6,
+                                         init_sl  => '0');                                               
+
+  SIGNAL mm_epcs_in_addr             : STD_LOGIC_VECTOR(g_epcs_addr_w-1 DOWNTO 0);
+  SIGNAL mm_epcs_in_rden             : STD_LOGIC;
+  SIGNAL mm_epcs_in_read_evt         : STD_LOGIC;
+  SIGNAL mm_epcs_in_write_evt        : STD_LOGIC;  
+  SIGNAL mm_epcs_in_sector_erase_evt : STD_LOGIC;  
+
+  SIGNAL mm_busy                     : STD_LOGIC;
+
+BEGIN
+
+  p_mm_reg : PROCESS (mm_rst, mm_clk)
+  BEGIN
+    IF mm_rst = '1' THEN
+      -- Read access
+      sla_out   <= c_mem_miso_rst;
+      -- Write access, register values
+      mm_epcs_in_addr <= (OTHERS=>'0');
+      mm_epcs_in_rden <= '0';
+    ELSIF rising_edge(mm_clk) THEN
+      -- Read access defaults
+      sla_out.rdval <= '0';
+      
+      -- Write event defaults
+      mm_epcs_in_read_evt         <= '0';
+      mm_epcs_in_write_evt        <= '0';
+      mm_epcs_in_sector_erase_evt <= '0';
+
+      -- Write access: set register value
+      IF sla_in.wr = '1' THEN
+        CASE TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
+          -- Write Block Sync
+          WHEN 0 => 
+            mm_epcs_in_addr <= sla_in.wrdata(g_epcs_addr_w-1 DOWNTO 0);
+          WHEN 1 => 
+            mm_epcs_in_rden <= sla_in.wrdata(0);
+          WHEN 2 => 
+            mm_epcs_in_read_evt <= sla_in.wrdata(0);
+          WHEN 3 => 
+            mm_epcs_in_write_evt <= sla_in.wrdata(0);
+          WHEN 4 => 
+            mm_epcs_in_sector_erase_evt <= sla_in.wrdata(0);
+          WHEN OTHERS => NULL;  -- unused MM addresses
+        END CASE;
+        
+      -- Read access: get register value
+      ELSIF sla_in.rd = '1' THEN
+        sla_out       <= c_mem_miso_rst;    -- set unused rddata bits to '0' when read
+        sla_out.rdval <= '1';               -- c_mm_reg.latency = 1
+        CASE TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
+          WHEN 5 =>            
+            sla_out.rddata(0) <= epcs_out_busy;
+          WHEN OTHERS => NULL;  -- unused MM addresses
+        END CASE;
+      END IF;
+    END IF;
+  END PROCESS;
+
+  u_spulse_epcs_read : ENTITY common_lib.common_spulse
+  PORT MAP (
+    in_rst    => mm_rst,
+    in_clk    => mm_clk,
+    in_pulse  => mm_epcs_in_read_evt,
+    in_busy   => OPEN,
+    out_rst   => epcs_rst,
+    out_clk   => epcs_clk,
+    out_pulse => epcs_in_read_evt
+  );
+
+  u_spulse_epcs_write : ENTITY common_lib.common_spulse
+  PORT MAP (
+    in_rst    => mm_rst,
+    in_clk    => mm_clk,
+    in_pulse  => mm_epcs_in_write_evt,
+    in_busy   => OPEN,
+    out_rst   => epcs_rst,
+    out_clk   => epcs_clk,
+    out_pulse => epcs_in_write_evt
+  );
+
+  u_spulse_epcs_sector_erase : ENTITY common_lib.common_spulse
+  PORT MAP (
+    in_rst    => mm_rst,
+    in_clk    => mm_clk,
+    in_pulse  => mm_epcs_in_sector_erase_evt,
+    in_busy   => OPEN,
+    out_rst   => epcs_rst,
+    out_clk   => epcs_clk,
+    out_pulse => epcs_in_sector_erase_evt
+  );
+
+  epcs_in_addr <= mm_epcs_in_addr;
+  epcs_in_rden <= mm_epcs_in_rden;
+
+END rtl;
+

libraries/io/epcs/src/vhdl/mms_epcs.vhd

@@ -35,6 +35,8 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
+USE tech_flash_lib.tech_flash_component_pkg.ALL;
+
 
 ENTITY mms_epcs IS
   GENERIC (
@@ -74,7 +76,7 @@ ARCHITECTURE str OF mms_epcs IS
   CONSTANT c_epcs_page_size            : NATURAL := 256;
   CONSTANT c_user_data_w               : NATURAL := c_word_w;
   CONSTANT c_epcs_data_w               : NATURAL := 8;
-  CONSTANT c_epcs_addr_w               : NATURAL := 24;
+  CONSTANT c_epcs_addr_w               : NATURAL := tech_flash_addr_w(g_technology);
 
   CONSTANT c_fifo_depth_bits           : NATURAL := c_epcs_page_size*c_epcs_data_w;  
   -- FIFO depths relative to epcs and user data widths
@@ -136,6 +138,9 @@ ARCHITECTURE str OF mms_epcs IS
 BEGIN
 
   u_epcs_reg: ENTITY work.epcs_reg
+  GENERIC MAP (
+    g_epcs_addr_w => c_epcs_addr_w
+  )
   PORT MAP (       
     mm_rst                   => mm_rst, 
     mm_clk                   => mm_clk,