- wr_nof_chunks has been removed. Write access is reduced to a singel access.

- Write state is heavily simplified. 

libraries/base/reorder/src/vhdl/reorder_sequencer.vhd

@@ -30,7 +30,7 @@
 --              The generics are interpreted as follows: 
 --
 --              - wr_chunksize is the number of samples that are written during a write access.
---              - wr_nof_chunks is the number of write accesses performed during a write period
+--                A write access always consists of 1 access. 
 --              - rd_chunksize is the number of samples that are read during a read access.
 --              - rd_nof_chunks is the number of read accesses performed during a read period
 --              - rd_interval defines the number of blocks in between two consecutive reads. 
@@ -42,7 +42,6 @@
 --              The example shows the following configuration: 
 --
 --              wr_chunksize    : POSITIVE := 8
---              wr_nof_chunks   : POSITIVE := 1;              
 --              rd_chunksize    : POSITIVE := 4;  
 --              rd_nof_chunks   : POSITIVE := 2;  
 --              rd_interval     : POSITIVE := 2;            
@@ -119,10 +118,9 @@ END reorder_sequencer;
 
 ARCHITECTURE rtl OF reorder_sequencer IS
   
-  CONSTANT c_blocksize          : POSITIVE := g_reorder_seq.wr_nof_chunks * (g_reorder_seq.wr_chunksize + g_reorder_seq.gapsize);  
+  CONSTANT c_blocksize          : POSITIVE := g_reorder_seq.wr_chunksize + g_reorder_seq.gapsize;  
   CONSTANT c_page_size          : POSITIVE := c_blocksize * g_reorder_seq.nof_blocks;
   CONSTANT c_rd_block_increment : POSITIVE := c_blocksize * g_reorder_seq.rd_interval;
-  CONSTANT c_nof_wr_access      : POSITIVE := g_reorder_seq.wr_nof_chunks * g_reorder_seq.nof_blocks;
   CONSTANT c_address_w          : POSITIVE := ceil_log2(2*c_page_size);    
   CONSTANT c_address_shift_w    : POSITIVE := ceil_log2(g_data_w_ratio);    
   
@@ -135,12 +133,7 @@ ARCHITECTURE rtl OF reorder_sequencer IS
     wr_not_rd        : STD_LOGIC;
     rd_block_offset  : NATURAL;
     rd_chunks_offset : NATURAL;
-    rd_block_cnt     : NATURAL;
-    rd_chunks_cnt    : NATURAL;
     wr_block_offset  : NATURAL;
-    wr_chunks_offset : NATURAL;
-    wr_block_cnt     : NATURAL;
-    wr_chunks_cnt    : NATURAL;
     switch_cnt       : NATURAL;   -- Counter that counts the write and read accesses to determine the switch between read and write phase. 
     page_cnt         : NATURAL;   -- Counter that counts the number of write accesses to determuine the page-swap. 
     first_write      : STD_LOGIC;
@@ -156,7 +149,7 @@ BEGIN
   ---------------------------------------------------------------
   -- CHECK IF PROVIDED GENERICS ARE ALLOWED. 
   ---------------------------------------------------------------
-  ASSERT NOT((g_reorder_seq.wr_nof_chunks*g_reorder_seq.wr_chunksize) /= (g_reorder_seq.rd_nof_chunks*g_reorder_seq.rd_chunksize) AND rising_edge(dp_clk)) REPORT "Total write configuration is different from total read configuration!!!" SEVERITY FAILURE;
+  ASSERT NOT(g_reorder_seq.wr_chunksize /= (g_reorder_seq.rd_nof_chunks*g_reorder_seq.rd_chunksize) AND rising_edge(dp_clk)) REPORT "Total write configuration is different from total read configuration!!!" SEVERITY FAILURE;
     
   p_comb : PROCESS(r, dp_rst, done)
     VARIABLE v : reg_type;
@@ -175,44 +168,24 @@ BEGIN
       WHEN s_first_write =>  
         v.wr_not_rd  := '1'; 
         v.ddr3_en    := '1'; 
-        v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset, c_address_w);
+        v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset, c_address_w);
         v.burstsize  := TO_UVEC(g_reorder_seq.wr_chunksize, c_address_w);
-        v.switch_cnt := r.switch_cnt + 1;
         v.state      := s_wait_wr;
         
       WHEN s_write =>  
         IF(done = '1') THEN 
           v.wr_not_rd  := '1'; 
           v.ddr3_en    := '1';
-          v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset + r.wr_chunks_offset, c_address_w);                   
+          v.start_addr := TO_UVEC(r.wr_page_offset + r.wr_block_offset, c_address_w);                   
           v.burstsize  := TO_UVEC(g_reorder_seq.wr_chunksize, c_address_w);
-          v.switch_cnt := r.switch_cnt + 1;
           v.state      := s_wait_wr; 
         END IF;
 
       WHEN s_wait_wr =>      
-        v.page_cnt := r.page_cnt + 1;
-        IF(r.wr_block_cnt = g_reorder_seq.nof_blocks-1 AND r.wr_chunks_cnt = g_reorder_seq.wr_nof_chunks-1) THEN 
-          v.wr_block_offset  := 0;
-          v.wr_chunks_offset := 0;
-          v.wr_block_cnt     := 0;
-          v.wr_chunks_cnt    := 0;
-        ELSIF(r.wr_block_cnt = g_reorder_seq.nof_blocks-1) THEN 
-          v.wr_block_offset  := 0;
-          v.wr_chunks_offset := r.wr_chunks_offset + g_reorder_seq.wr_chunksize;
-          v.wr_block_cnt     := 0; 
-          v.wr_chunks_cnt    := r.wr_chunks_cnt + 1;
-        ELSE 
         v.wr_block_offset := r.wr_block_offset + c_blocksize;
-          v.wr_block_cnt    := r.wr_block_cnt + 1;
-        END IF;          
-        
-        IF(r.switch_cnt = g_reorder_seq.wr_nof_chunks) THEN
+        v.page_cnt        := r.page_cnt + 1;
         v.switch_cnt      := 0; 
         v.state           := s_read;
-        ELSE
-          v.state := s_write;
-        END IF;  
       
       WHEN s_read => 
         IF(done = '1') THEN 
@@ -232,23 +205,19 @@ BEGIN
         
         IF(r.rd_block_offset + c_rd_block_increment >= c_page_size) THEN
           v.rd_chunks_offset := r.rd_chunks_offset + g_reorder_seq.rd_chunksize;        
-          v.rd_chunks_cnt    := r.rd_chunks_cnt + 1;                    
-        ELSE 
-          v.rd_block_cnt    := r.rd_block_cnt + 1;
         END IF;
 
         IF(r.switch_cnt = g_reorder_seq.rd_nof_chunks) THEN 
           v.switch_cnt := 0; 
           v.state      := s_write;
-          IF(r.page_cnt = c_nof_wr_access) THEN 
+          IF(r.page_cnt = g_reorder_seq.nof_blocks) THEN 
             v.rd_page_offset   := r.wr_page_offset;
             v.wr_page_offset   := r.rd_page_offset;
             v.page_cnt         := 0;  
             v.first_write      := '0';
             v.rd_block_offset  := 0;
             v.rd_chunks_offset := 0;
-            v.rd_block_cnt     := 0;
-            v.rd_chunks_cnt    := 0;    
+            v.wr_block_offset  := 0;
           END IF; 
         ELSE
           v.state := s_read;
@@ -267,13 +236,8 @@ BEGIN
       v.ddr3_en          := '0';
       v.wr_not_rd        := '0';
       v.wr_block_offset  := 0;
-      v.wr_chunks_offset := 0;
-      v.wr_block_cnt     := 0;
-      v.wr_chunks_cnt    := 0;
       v.rd_block_offset  := 0;
       v.rd_chunks_offset := 0;
-      v.rd_block_cnt     := 0;
-      v.rd_chunks_cnt    := 0;
       v.start_addr       := (OTHERS => '0');
       v.burstsize        := (OTHERS => '0');
       v.first_write      := '1';