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Commit 692ddc62 authored by Eric Kooistra's avatar Eric Kooistra
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Added ALTERA_HW_TCL_KEEP_TEMP_FILES to try to avoid an Quartus warning with Qsys.

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tools/quartus/quartus_generic.sh
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...@@ -40,6 +40,9 @@ ${NIOSDIR}/bin:\ ...@@ -40,6 +40,9 @@ ${NIOSDIR}/bin:\
${NIOSDIR}/bin/gnu/H-i686-pc-linux-gnu/bin:\ ${NIOSDIR}/bin/gnu/H-i686-pc-linux-gnu/bin:\
${NIOSDIR}/sdk2/bin ${NIOSDIR}/sdk2/bin
# Qsys
export ALTERA_HW_TCL_KEEP_TEMP_FILES=1
# User synthesis timestamp in FPGA image # User synthesis timestamp in FPGA image
export UNB_COMPILE_STAMPS=1 export UNB_COMPILE_STAMPS=1
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