Use stratixiv 200 MHz PLL from tech_pll/. Only support g_sel=0,1 (skipped...

Use stratixiv 200 MHz PLL from tech_pll/. Only support g_sel=0,1 (skipped g_sel=2, because it is not used in UniBoard1 designs).

boards/uniboard1/libraries/unb1_board/hdllib.cfg

 hdl_lib_name = unb1_board
 hdl_library_clause_name = unb1_board_lib
-hdl_lib_uses = common dp diag uth ppsh i2c tr_nonbonded eth remu
+hdl_lib_uses = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
-    $UNB/Firmware/designs/unb_common/../../modules/MegaWizard/pll/clk200_pll.vhd
-    $UNB/Firmware/designs/unb_common/../../modules/MegaWizard/pll/clk200_pll_c0_8.vhd
-    $UNB/Firmware/designs/unb_common/../../modules/MegaWizard/pll/clk200_pll_pq.vhd
-    $UNB/Firmware/designs/unb_common/../../modules/MegaWizard/pll/clk200_pll_p6.vhd
-    
     src/vhdl/unb1_board_pkg.vhd
     src/vhdl/unb1_board_system_info.vhd
     src/vhdl/unb1_board_system_info_reg.vhd

boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd

@@ -25,7 +25,7 @@
 --   . ctrl_unb1_board.vhd with e.g. 1GbE and PPS
 --   . node_<design_name>.vhd with the actual functionality of <design_name>
 
-LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, tech_tse_lib, eth_lib, remu_lib;
+LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -33,6 +33,7 @@ USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE work.unb1_board_pkg.ALL;
 USE i2c_lib.i2c_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
 USE tech_tse_lib.tech_tse_pkg.ALL;
 USE eth_lib.eth_pkg.ALL;
 
@@ -41,6 +42,7 @@ ENTITY ctrl_unb1_board IS
     ----------------------------------------------------------------------------
     -- General
     ----------------------------------------------------------------------------
+    g_technology     : NATURAL := c_tech_stratixiv;
     g_sim            : BOOLEAN := FALSE;
     g_design_name    : STRING := "UNUSED";
     g_fw_version     : t_unb1_board_fw_version := (0, 0);  -- firmware version x.y
@@ -312,6 +314,7 @@ BEGIN
   gen_pll: IF g_dp_clk_use_pll = TRUE GENERATE
     u_unb1_board_clk200_pll : ENTITY work.unb1_board_clk200_pll
     GENERIC MAP (
+      g_technology          => g_technology,
       g_sel                 => c_dp_clk_pll_sel,
       g_clk200_phase_shift  => g_dp_clk_phase,
       g_clk_vec_w           => g_dp_phs_clk_vec_w,
@@ -584,6 +587,7 @@ BEGIN
 
     u_mac : ENTITY eth_lib.eth
     GENERIC MAP (
+      g_technology         => g_technology,
       g_cross_clock_domain => g_udp_offload
     )
     PORT MAP (

boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd

@@ -20,9 +20,10 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib, tech_pll_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
 
 -- Purpose: PLL for UniBoard node CLK input @ 200 MHz
 -- Description:
@@ -91,8 +92,9 @@ USE common_lib.common_pkg.ALL;
 
 ENTITY unb1_board_clk200_pll IS
   GENERIC (
+    g_technology          : NATURAL := c_tech_stratixiv;
     g_sel                 : NATURAL := 0;
-    g_operation_mode      : STRING  := "NORMAL";  -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for
+    g_operation_mode      : STRING  := "NORMAL";  -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
     
     -- g_sel=0 for clk200_pll.vhd
     g_clk200_phase_shift  : STRING := "0";  -- default use 0 degrees, see clk200_pll.vhd for other phase values
@@ -114,13 +116,7 @@ ENTITY unb1_board_clk200_pll IS
     g_clk3_divide_by      : NATURAL := 32;          -- = clk 200/32 MHz 
     g_clk4_divide_by      : NATURAL := 32;          -- = clk 200/32 MHz 
     g_clk5_divide_by      : NATURAL := 32;          -- = clk 200/32 MHz 
-    g_clk6_divide_by      : NATURAL := 32;          -- = clk 200/32 MHz 
-    
-    -- g_sel=2 for clk200_pll_pq.vhd
-    g_clkp_divide_by      : NATURAL := 32;      -- = st_clkp
-    g_clkq_divide_by      : NATURAL := 32;      -- = st_clkq
-    g_clkp_phase_shift    : STRING :=    "0";  -- = 000 for st_clkp relative to c0 = st_clk200 with phase 0
-    g_clkq_phase_shift    : STRING := "1250"   -- = 090 for st_clkq relative to c0 = st_clk200 with phase 0    
+    g_clk6_divide_by      : NATURAL := 32           -- = clk 200/32 MHz     
   );
   PORT (
     -- It depends on g_sel which outputs are actually available
@@ -135,10 +131,7 @@ ENTITY unb1_board_clk200_pll IS
     st_clk400   : OUT STD_LOGIC;  -- PLL c2 = 0                     degrees phase offset to input clk200
     st_rst400   : OUT STD_LOGIC;
     -- . g_sel=1
-    st_clk_vec  : OUT STD_LOGIC_VECTOR(g_clk_vec_w-1 DOWNTO 0); -- PLL c6-c1
-    -- . g_sel=2
-    st_clkp     : OUT STD_LOGIC;  -- PLL c1 = divided clk with g_clkp_phase_shift degrees phase offset to input clk200
-    st_clkq     : OUT STD_LOGIC   -- PLL c2 = divided clk with g_clkq_phase_shift degrees phase offset to input clk200, typically 90 degrees delayed st_clkp
+    st_clk_vec  : OUT STD_LOGIC_VECTOR(g_clk_vec_w-1 DOWNTO 0)  -- PLL c6-c1
   );
 END unb1_board_clk200_pll;
 
@@ -173,8 +166,9 @@ BEGIN
   st_clk_vec <= i_st_clk_vec(g_clk_vec_w-1 DOWNTO 0);
     
   gen_0 : IF g_sel=0 GENERATE
-    u_st_pll : ENTITY work.clk200_pll
+    u_st_pll : ENTITY tech_pll_lib.tech_pll_clk200
     GENERIC MAP (
+      g_technology       => g_technology,
       g_operation_mode   => g_operation_mode,
       g_clk0_phase_shift => g_clk200_phase_shift,
       g_clk1_phase_shift => g_clk200p_phase_shift
@@ -192,8 +186,9 @@ BEGIN
   gen_1 : IF g_sel=1 GENERATE
     i_st_clk200p <= i_st_clk_vec(0);
     
-    u_st_pll_p6 : ENTITY work.clk200_pll_p6
+    u_st_pll_p6 : ENTITY tech_pll_lib.tech_pll_clk200_p6
     GENERIC MAP (
+      g_technology       => g_technology,
       g_operation_mode   => g_operation_mode,
       g_clk0_phase_shift => g_clk0_phase_shift,
       g_clk1_used        => c_clk1_used,
@@ -229,26 +224,6 @@ BEGIN
     );
   END GENERATE;
   
-  gen_2 : IF g_sel=2 GENERATE
-    u_st_pll : ENTITY work.clk200_pll_pq
-    GENERIC MAP (
-      g_operation_mode   => g_operation_mode,
-      g_clk0_phase_shift => g_clk200_phase_shift,
-      g_clk1_divide_by   => g_clkp_divide_by,
-      g_clk2_divide_by   => g_clkq_divide_by,
-      g_clk1_phase_shift => g_clkp_phase_shift,
-      g_clk2_phase_shift => g_clkq_phase_shift
-    )
-  	PORT MAP (
-      areset  => arst,
-      inclk0  => clk200,
-      c0      => i_st_clk200,
-      c1      => st_clkp,
-      c2      => st_clkq,
-      locked  => st_locked
-    );
-  END GENERATE;
-  
   -- Release clock domain resets after some clock cycles when the PLL has locked  
   st_locked_n <= NOT st_locked;
   

boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd

@@ -63,8 +63,6 @@ ARCHITECTURE tb OF tb_unb1_board_clk200_pll IS
   
   SIGNAL dp_clk200      : STD_LOGIC;
   SIGNAL dp_rst200      : STD_LOGIC;
-  SIGNAL dp_clkp        : STD_LOGIC;
-  SIGNAL dp_clkq        : STD_LOGIC;
   
   SIGNAL st_clk_vec     : STD_LOGIC_VECTOR(c_clk_vec_w-1 DOWNTO 0);  -- PLL c6-c1
   
@@ -115,9 +113,8 @@ BEGIN
   GENERIC MAP (
     g_sel                 => 1,  -- g_sel=0 for clk200_pll.vhd
                                  -- g_sel=1 for clk200_pll_p6.vhd
-                                 -- g_sel=2 for clk200_pll_pq.vhd
     g_clk200_phase_shift  => "0",
-    -- g_sel=2 for clk200_pll_p6.vhd
+    -- g_sel=1 for clk200_pll_p6.vhd
     g_clk0_phase_shift    =>    "0",
     g_clk_vec_w           => c_clk_vec_w,
     g_clk1_phase_shift    =>    "0",
@@ -138,30 +135,8 @@ BEGIN
     clk200     => ext_clk,
     st_clk200  => dp_clk200,
     st_rst200  => dp_rst200,
-    -- . g_sel=2
+    -- . g_sel=1
     st_clk_vec => st_clk_vec
   );
   
-  dut_pq : ENTITY work.unb1_board_clk200_pll
-  GENERIC MAP (
-    g_sel                 => 2,  -- g_sel=0 for clk200_pll.vhd
-                                 -- g_sel=1 for clk200_pll_p6.vhd
-                                 -- g_sel=2 for clk200_pll_pq.vhd
-    -- g_sel=0 for clk200_pll.vhd
-    g_clk200_phase_shift  => "0",
-    -- g_sel=1 for clk200_pll_pq.vhd
-    g_clkp_divide_by      => c_clk_div,
-    g_clkq_divide_by      => c_clk_div,
-    g_clkp_phase_shift    => "0",     -- =    0;  -- = 000 for st_clkp relative to c0 = st_clk200
-    g_clkq_phase_shift    => "1250"   -- = 1250;  -- = 090 for st_clkq relative to c0 = st_clk200
-  )
-  PORT MAP (
-    arst       => ext_rst,
-    clk200     => ext_clk,
-    st_clk200  => dp_clk200,
-    st_rst200  => dp_rst200,
-    st_clkp    => dp_clkp,
-    st_clkq    => dp_clkq
-  );
-  
 END tb;