-Added I/O model to multiplier.

libraries/base/common_mult/src/vhdl/common_complex_mult.vhd

@@ -47,6 +47,8 @@ USE technology_lib.technology_select_pkg.ALL;
 
 ENTITY common_complex_mult IS
   GENERIC (
+    g_sim              : BOOLEAN := FALSE;
+    g_sim_level        : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
     g_technology       : NATURAL  := c_tech_select_default;
     g_variant          : STRING := "IP";
     g_in_a_w           : POSITIVE;
@@ -109,6 +111,8 @@ BEGIN
 
   u_complex_mult : ENTITY tech_mult_lib.tech_complex_mult
   GENERIC MAP(
+    g_sim              => g_sim,
+    g_sim_level        => g_sim_level,
     g_technology       => g_technology,
     g_variant          => g_variant,
     g_in_a_w           => g_in_a_w,

libraries/technology/mult/tech_complex_mult.vhd

@@ -36,6 +36,8 @@ LIBRARY ip_arria10_complex_mult_rtl_lib;
 
 ENTITY tech_complex_mult IS
   GENERIC (
+    g_sim              : BOOLEAN := TRUE;
+    g_sim_level        : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
     g_technology       : NATURAL  := c_tech_select_default;
     g_variant          : STRING := "IP";
     g_in_a_w           : POSITIVE;
@@ -78,9 +80,13 @@ ARCHITECTURE str of tech_complex_mult is
   SIGNAL mult_re   : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
   SIGNAL mult_im   : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
 
+  -- sim_model=1
+  SIGNAL result_re_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
+  SIGNAL result_im_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
+
 begin
 
-  gen_ip_stratixiv_ip : IF (g_technology=c_tech_stratixiv AND g_variant="IP") GENERATE
+  gen_ip_stratixiv_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="IP") GENERATE
 
     -- Adapt DSP input widths
     ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
@@ -107,7 +113,7 @@ begin
 
   END GENERATE;
    
-  gen_ip_stratixiv_rtl : IF (g_technology=c_tech_stratixiv AND g_variant="RTL") GENERATE
+  gen_ip_stratixiv_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="RTL") GENERATE
     u0 : ip_stratixiv_complex_mult_rtl
   GENERIC MAP(
     g_in_a_w           => g_in_a_w,
@@ -132,7 +138,7 @@ begin
     );
   END GENERATE;
 
-  gen_ip_arria10_ip : IF (g_technology=c_tech_arria10 AND g_variant="IP") GENERATE
+  gen_ip_arria10_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10 AND g_variant="IP") GENERATE
 
     -- Adapt DSP input widths
     ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
@@ -159,7 +165,7 @@ begin
 
   END GENERATE;
 
-  gen_ip_arria10_rtl : IF (g_technology=c_tech_arria10 AND g_variant="RTL") GENERATE
+  gen_ip_arria10_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10 AND g_variant="RTL") GENERATE
     u0 : ip_arria10_complex_mult_rtl
   GENERIC MAP(
     g_in_a_w           => g_in_a_w,
@@ -184,6 +190,50 @@ begin
     );
   END GENERATE;
 
+  -------------------------------------------------------------------------------
+  -- Model: forward concatenated inputs to the 'result' output
+  -- 
+  -- Example:
+  --                                    ______ 
+  -- Input B.real (in_br) = 0x1111 --> |      |
+  --        .imag (in_bi) = 0xBBBB --> |      |
+  --                                   | mult | --> Output result.real = 0x00000000
+  -- Input A.real (in_ar) = 0x0000 --> |      |                  .imag = 0xBBBBAAAA
+  --        .imag (in_ai) = 0xAAAA --> |______|
+  -- 
+  -- Note: this model is synthsizable as well.
+  -- 
+  -------------------------------------------------------------------------------
+  gen_sim_level_1 : IF g_sim=TRUE AND g_sim_level=1 GENERATE --FIXME: g_sim required? This is synthesizable.
+
+    result_re_undelayed <= in_br & in_ar;
+    result_im_undelayed <= in_bi & in_ai;
+
+    u_common_pipeline_re : entity common_lib.common_pipeline
+    generic map (
+      g_pipeline  => 3,
+      g_in_dat_w  => g_in_b_w+g_in_a_w,
+      g_out_dat_w => g_out_p_w
+    )
+    port map (
+      clk     => clk,
+      in_dat  => result_re_undelayed,
+      out_dat => result_re
+    );
+
+    u_common_pipeline_im : entity common_lib.common_pipeline
+    generic map (
+      g_pipeline  => 3,
+      g_in_dat_w  => g_in_b_w+g_in_a_w,
+      g_out_dat_w => g_out_p_w
+    )
+    port map (
+      clk     => clk,
+      in_dat  => result_im_undelayed,
+      out_dat => result_im
+    );
+
+  END GENERATE;
 
 end str;