fixed bug that caused wrong start address in sd_bsn_align_v2

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd

@@ -102,6 +102,7 @@ ARCHITECTURE str OF node_sdp_correlator IS
   SIGNAL quant_sosi_arr                : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
   SIGNAL dp_bsn_sync_scheduler_src_out : t_dp_sosi := c_dp_sosi_rst;
   SIGNAL xsel_sosi                     : t_dp_sosi := c_dp_sosi_rst;
+  SIGNAL xsel_data_sosi                : t_dp_sosi := c_dp_sosi_rst;
   SIGNAL local_sosi                    : t_dp_sosi := c_dp_sosi_rst;
 
   SIGNAL ring_mux_sosi                 : t_dp_sosi := c_dp_sosi_rst;
@@ -172,6 +173,14 @@ BEGIN
   ---------------------------------------------------------------
   -- Repack 32b to 64b 
   ---------------------------------------------------------------
+  -- repacking xsel re/im to data field.
+  p_wire_xsel_sosi : PROCESS(xsel_sosi)
+  BEGIN
+    xsel_data_sosi <= xsel_sosi;
+    xsel_data_sosi.data(                c_sdp_W_crosslet -1 DOWNTO 0)                <= xsel_sosi.re(c_sdp_W_crosslet-1 DOWNTO 0);
+    xsel_data_sosi.data(c_nof_complex * c_sdp_W_crosslet -1 DOWNTO c_sdp_W_crosslet) <= xsel_sosi.im(c_sdp_W_crosslet-1 DOWNTO 0);
+  END PROCESS;
+
   u_dp_repack_data_local : ENTITY dp_lib.dp_repack_data
   GENERIC MAP (
     g_in_dat_w      => c_data_w,
@@ -183,7 +192,7 @@ BEGIN
     rst => dp_rst,
     clk => dp_clk,
 
-    snk_in  => xsel_sosi,
+    snk_in  => xsel_data_sosi,
     src_out => local_sosi
   );
 
@@ -256,6 +265,7 @@ BEGIN
     g_block_size              => c_block_size,    
     g_data_w                  => c_data_w,    
     g_use_mm_output           => TRUE,   
+    g_rd_latency              => 1, -- Required for st_xst 
     -- for mms_dp_bsn_monitor_v2
     g_nof_clk_per_sync        => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
     g_nof_input_bsn_monitors  => g_P_sq,  
@@ -288,7 +298,6 @@ BEGIN
     mm_sosi     => crosslets_sosi,            
     mm_copi     => crosslets_copi,            
     mm_cipo_arr => crosslets_cipo_arr            
-
   );
 
   ---------------------------------------------------------------

applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd

@@ -262,7 +262,7 @@ BEGIN
   u_reorder_col_wide_select : ENTITY reorder_lib.reorder_col_wide_select
   GENERIC MAP (
     g_nof_inputs         => c_sdp_P_pfb,
-    g_dsp_data_w         => c_sdp_W_subband,
+    g_dsp_data_w         => c_sdp_W_crosslet,
     g_nof_ch_in          => c_sdp_N_sub * c_sdp_Q_fft,
     g_nof_ch_sel         => g_N_crosslets * c_sdp_S_pn
   )
@@ -282,7 +282,7 @@ BEGIN
   
   u_reorder_row_select : ENTITY reorder_lib.reorder_row_select
   GENERIC MAP (
-    g_dsp_data_w         => c_sdp_W_subband,
+    g_dsp_data_w         => c_sdp_W_crosslet,
     g_nof_inputs         => c_sdp_P_pfb,
     g_nof_outputs        => 1,
     g_pipeline_in        => 0, 

libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd

@@ -243,7 +243,8 @@ BEGIN
         -- . set address at start of block
         w.blk_pointer_slv := in_sosi_arr_p(I).bsn(c_blk_pointer_w-1 DOWNTO 0);
         w.product_slv := MULT_UVEC(w.blk_pointer_slv, c_block_size_slv);
-        v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(w.product_slv);
+        -- . resize to c_mem_ram.adr_w
+        v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(RESIZE_UVEC(w.product_slv, c_mem_ram.adr_w));
 
         -- . set filled flag at sop, so assume rest of block will follow in time
         v.filled_arr(I)(TO_UINT(w.blk_pointer_slv)) := '1';

libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd

@@ -106,7 +106,7 @@ ARCHITECTURE str OF mmp_dp_bsn_align_v2 IS
   --   init_sl   : STD_LOGIC;  -- optional, init all dat words to std_logic '0', '1' or 'X'
   CONSTANT c_mm_reg       : t_c_mem := (1, ceil_log2(g_nof_streams), 1, g_nof_streams, '0');
 
-  SIGNAL reg_wr           : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
+  SIGNAL reg_wr           : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS => '1');
   SIGNAL stream_en_arr    : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
 
   SIGNAL ref_sync         : STD_LOGIC;
@@ -121,7 +121,8 @@ BEGIN
   GENERIC MAP (
     g_cross_clock_domain   => TRUE,
     g_readback             => FALSE,
-    g_reg                  => c_mm_reg
+    g_reg                  => c_mm_reg,
+    g_init_reg             => (OTHERS => '1')
   )
   PORT MAP (
     -- Clocks and reset

libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd

@@ -130,13 +130,19 @@ ARCHITECTURE tb OF tb_dp_bsn_align_v2 IS
 
   -- Return input delay as function of inputs stream index I
   FUNCTION func_input_delay(I : NATURAL) RETURN NATURAL IS
+    VARIABLE v : NATURAL;
   BEGIN
-    RETURN c_diff_delay * I / (g_nof_streams - 1);
+    IF g_nof_streams > 1 THEN
+      v := c_diff_delay * I / (g_nof_streams - 1);
+    ELSE
+      v := 0;
+    END IF;
+    RETURN v;
   END;
 
   CONSTANT c_gap_size                 : NATURAL := g_block_period - g_block_size;
 
-  CONSTANT c_lost_bsn_stream_id       : NATURAL := 1;  -- fixed use stream 1 to verify g_lost_bsn_id
+  CONSTANT c_lost_bsn_stream_id       : NATURAL := sel_a_b(g_nof_streams > 1, 1, 0);  -- fixed use stream 1 to verify g_lost_bsn_id. Use 0 for g_nof_streams = 1.
 
   -- In the tb only support MM interface verification for c_nof_aligners_max = 1
   CONSTANT c_nof_aligners_max  : POSITIVE := sel_a_b(g_use_mm_output, 1, g_nof_aligners_max);

libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd

@@ -66,7 +66,9 @@ BEGIN
   -- g_tb_nof_blocks        : NATURAL := 10       -- number of input blocks per restart
 
   u_mm_output               : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0,  TRUE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_mm_output_single        : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (1, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0,  TRUE, 0, 0, 1,  0, 2, c_nof_blk);
   u_dp_output               : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
+  u_dp_output_single        : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (1, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
   u_dp_output_p1            : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 1, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 1, 1, 1,  0, 2, c_nof_blk);
   u_bsn_lat_max_2           : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 2, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);
   u_bsn_lat_max_3           : ENTITY work.tb_dp_bsn_align_v2 GENERIC MAP (2, 3, 1, c_block, c_period, 32, 16, 17, 0, 0,  0, FALSE, 0, 0, 1,  0, 2, c_nof_blk);

libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd

@@ -59,18 +59,10 @@ ARCHITECTURE rtl OF st_xsq_dp_to_mm IS
   SIGNAL ram_wr_mosi   :  t_mem_mosi := c_mem_mosi_rst;
 
   SIGNAL reg_sosi_info : t_dp_sosi := c_dp_sosi_rst;
-  SIGNAL in_sosi_rewired : t_dp_sosi := c_dp_sosi_rst;
   SIGNAL next_page : STD_LOGIC;
 
 BEGIN
 
-  p_in_sosi : PROCESS(in_sosi)
-  BEGIN
-    in_sosi_rewired <= in_sosi;
-    in_sosi_rewired.data(                g_dsp_data_w -1 DOWNTO 0)            <= in_sosi.re(g_dsp_data_w-1 DOWNTO 0);
-    in_sosi_rewired.data(c_nof_complex * g_dsp_data_w -1 DOWNTO g_dsp_data_w) <= in_sosi.im(g_dsp_data_w-1 DOWNTO 0);
-  END PROCESS;
-
   u_dp_block_to_mm : ENTITY dp_lib.dp_block_to_mm
   GENERIC MAP(
     g_data_size => 1,
@@ -82,7 +74,7 @@ BEGIN
     clk => clk,
     start_address => 0,
     mm_mosi => ram_wr_mosi,
-    in_sosi => in_sosi_rewired
+    in_sosi => in_sosi
   );
 
   u_common_paged_ram_r_w : ENTITY common_lib.common_paged_ram_r_w