modifiications unb1 -> unb2

boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd

@@ -25,7 +25,7 @@ USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE unb2_board_lib.unb2_board_pkg.ALL;
-USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
 USE mm_lib.mm_file_pkg.ALL;
 USE mm_lib.mm_file_unb_pkg.ALL;
 USE work.qsys_unb2_minimal_pkg.ALL;
@@ -106,6 +106,7 @@ ARCHITECTURE str OF mmm_unb2_minimal IS
   CONSTANT c_epcs_clk_period : TIME := 50 ns;  -- 20 MHz
 
   CONSTANT c_sim_node_nr   : NATURAL := g_sim_node_nr;
+  CONSTANT c_sim_node_type : STRING(1 TO 2):= "PN";
 
   SIGNAL i_mm_clk   : STD_LOGIC := '1';
   SIGNAL i_epcs_clk : STD_LOGIC := '1';
@@ -190,19 +191,19 @@ BEGIN
       -- the_avs_eth_0
       coe_clk_export_from_the_avs_eth_0             => OPEN,
       coe_reset_export_from_the_avs_eth_0           => eth1g_mm_rst,
-      coe_tse_address_export_from_the_avs_eth_0     => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+      coe_tse_address_export_from_the_avs_eth_0     => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
       coe_tse_write_export_from_the_avs_eth_0       => eth1g_tse_mosi.wr,
       coe_tse_writedata_export_from_the_avs_eth_0   => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
       coe_tse_read_export_from_the_avs_eth_0        => eth1g_tse_mosi.rd,
       coe_tse_readdata_export_to_the_avs_eth_0      => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_tse_waitrequest_export_to_the_avs_eth_0   => eth1g_tse_miso.waitrequest,
-      coe_reg_address_export_from_the_avs_eth_0     => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+      coe_reg_address_export_from_the_avs_eth_0     => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
       coe_reg_write_export_from_the_avs_eth_0       => eth1g_reg_mosi.wr,
       coe_reg_writedata_export_from_the_avs_eth_0   => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
       coe_reg_read_export_from_the_avs_eth_0        => eth1g_reg_mosi.rd,
       coe_reg_readdata_export_to_the_avs_eth_0      => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_irq_export_to_the_avs_eth_0               => eth1g_reg_interrupt,
-      coe_ram_address_export_from_the_avs_eth_0     => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+      coe_ram_address_export_from_the_avs_eth_0     => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
       coe_ram_write_export_from_the_avs_eth_0       => eth1g_ram_mosi.wr,
       coe_ram_writedata_export_from_the_avs_eth_0   => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
       coe_ram_read_export_from_the_avs_eth_0        => eth1g_ram_mosi.rd,
@@ -211,7 +212,7 @@ BEGIN
       -- the_reg_unb_sens
       coe_clk_export_from_the_reg_unb_sens          => OPEN,
       coe_reset_export_from_the_reg_unb_sens        => OPEN,
-      coe_address_export_from_the_reg_unb_sens      => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+      coe_address_export_from_the_reg_unb_sens      => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
       coe_read_export_from_the_reg_unb_sens         => reg_unb_sens_mosi.rd,
       coe_readdata_export_to_the_reg_unb_sens       => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_write_export_from_the_reg_unb_sens        => reg_unb_sens_mosi.wr,
@@ -223,7 +224,7 @@ BEGIN
       -- the_pio_pps
       coe_clk_export_from_the_pio_pps               => OPEN,
       coe_reset_export_from_the_pio_pps             => OPEN,
-      coe_address_export_from_the_pio_pps           => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1),  -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+      coe_address_export_from_the_pio_pps           => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1),  -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
       coe_read_export_from_the_pio_pps              => reg_ppsh_mosi.rd,
       coe_readdata_export_to_the_pio_pps            => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_write_export_from_the_pio_pps             => reg_ppsh_mosi.wr,
@@ -232,7 +233,7 @@ BEGIN
       -- the_pio_system_info: actually a avs_common_mm instance
       coe_clk_export_from_the_pio_system_info       => OPEN,
       coe_reset_export_from_the_pio_system_info     => OPEN,
-      coe_address_export_from_the_pio_system_info   => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), 
+      coe_address_export_from_the_pio_system_info   => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), 
       coe_read_export_from_the_pio_system_info      => reg_unb_system_info_mosi.rd,
       coe_readdata_export_to_the_pio_system_info    => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_write_export_from_the_pio_system_info     => reg_unb_system_info_mosi.wr,
@@ -241,7 +242,7 @@ BEGIN
       -- the_rom_system_info
       coe_clk_export_from_the_rom_system_info       => OPEN,
       coe_reset_export_from_the_rom_system_info     => OPEN,
-      coe_address_export_from_the_rom_system_info   => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
+      coe_address_export_from_the_rom_system_info   => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
       coe_read_export_from_the_rom_system_info      => rom_unb_system_info_mosi.rd,
       coe_readdata_export_to_the_rom_system_info    => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_write_export_from_the_rom_system_info     => rom_unb_system_info_mosi.wr,
@@ -290,7 +291,7 @@ BEGIN
       -- the_reg_epcs
       coe_clk_export_from_the_reg_epcs              => OPEN,
       coe_reset_export_from_the_reg_epcs            => OPEN,
-      coe_address_export_from_the_reg_epcs          => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+      coe_address_export_from_the_reg_epcs          => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
       coe_read_export_from_the_reg_epcs             => reg_epcs_mosi.rd,
       coe_readdata_export_to_the_reg_epcs           => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_write_export_from_the_reg_epcs            => reg_epcs_mosi.wr,
@@ -299,7 +300,7 @@ BEGIN
       -- the_reg_remu
       coe_clk_export_from_the_reg_remu              => OPEN,
       coe_reset_export_from_the_reg_remu            => OPEN,
-      coe_address_export_from_the_reg_remu          => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+      coe_address_export_from_the_reg_remu          => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
       coe_read_export_from_the_reg_remu             => reg_remu_mosi.rd,
       coe_readdata_export_to_the_reg_remu           => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
       coe_write_export_from_the_reg_remu            => reg_remu_mosi.wr,