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Commit 67a4ee73 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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this design has 48 back and 24 front channels 10GbE. Succesful synthesis

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boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
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− 106
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...@@ -47,10 +47,10 @@ ENTITY unb2_test IS ...@@ -47,10 +47,10 @@ ENTITY unb2_test IS
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_factory_image : BOOLEAN := FALSE; g_factory_image : BOOLEAN := FALSE;
g_nof_streams_qsfp : NATURAL := 4;--c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w; g_nof_streams_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
g_nof_streams_ring : NATURAL := 0;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w; g_nof_streams_ring : NATURAL := 0;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
g_nof_streams_back0: NATURAL := 0;--c_unb2_board_tr_back.bus_w; g_nof_streams_back0: NATURAL := c_unb2_board_tr_back.bus_w;
g_nof_streams_back1: NATURAL := 0 --c_unb2_board_tr_back.bus_w g_nof_streams_back1: NATURAL := c_unb2_board_tr_back.bus_w
); );
PORT ( PORT (
-- GENERAL -- GENERAL
...@@ -80,8 +80,8 @@ ENTITY unb2_test IS ...@@ -80,8 +80,8 @@ ENTITY unb2_test IS
BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
-- back transceivers -- back transceivers
--BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0); BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0); BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0); BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0); BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0); BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_back.i2c_w-1 downto 0);
...@@ -98,16 +98,16 @@ ENTITY unb2_test IS ...@@ -98,16 +98,16 @@ ENTITY unb2_test IS
-- front transceivers -- front transceivers
QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0); QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0); QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
...@@ -589,7 +589,7 @@ BEGIN ...@@ -589,7 +589,7 @@ BEGIN
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP ( GENERIC MAP (
g_nof_output_streams => g_nof_streams, g_nof_streams => g_nof_streams,
g_buf_dat_w => c_data_w, g_buf_dat_w => c_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)), g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(c_data_w), -- counter_data_32_0.hex, counter_data_32_1.hex, ... g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(c_data_w), -- counter_data_32_0.hex, counter_data_32_1.hex, ...
...@@ -820,58 +820,58 @@ BEGIN ...@@ -820,58 +820,58 @@ BEGIN
serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
); );
-- u_tr_10GbE_back0: ENTITY unb2_board_lib.unb2_board_10gbe -- Lower Back lines u_tr_10GbE_back0: ENTITY unb2_board_lib.unb2_board_10gbe -- Lower Back lines
-- GENERIC MAP ( GENERIC MAP (
-- g_technology => g_technology, g_technology => g_technology,
-- g_sim => g_sim, g_sim => g_sim,
-- g_sim_level => 1, g_sim_level => 1,
-- g_nof_macs => g_nof_streams_back0, g_nof_macs => g_nof_streams_back0,
-- g_tx_fifo_fill => c_def_10GbE_block_size, g_tx_fifo_fill => c_def_10GbE_block_size,
-- g_tx_fifo_size => c_def_10GbE_block_size*2 g_tx_fifo_size => c_def_10GbE_block_size*2
-- ) )
-- PORT MAP ( PORT MAP (
-- tr_ref_clk => BCK_REF_CLK, tr_ref_clk => BCK_REF_CLK,
-- mm_rst => mm_rst, mm_rst => mm_rst,
-- mm_clk => mm_clk, mm_clk => mm_clk,
-- reg_mac_mosi => reg_tr_10GbE_back0_mosi, reg_mac_mosi => reg_tr_10GbE_back0_mosi,
-- reg_mac_miso => reg_tr_10GbE_back0_miso, reg_mac_miso => reg_tr_10GbE_back0_miso,
-- dp_rst => dp_rst, dp_rst => dp_rst,
-- dp_clk => dp_clk, dp_clk => dp_clk,
-- src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring), src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
-- src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring), src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
-- snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring), snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
-- snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring), snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO g_nof_streams_qsfp+g_nof_streams_ring),
--
-- serial_tx_arr => i_serial_10G_tx_back0_arr, serial_tx_arr => i_serial_10G_tx_back0_arr,
-- serial_rx_arr => i_serial_10G_rx_back0_arr serial_rx_arr => i_serial_10G_rx_back0_arr
-- ); );
-- u_tr_10GbE_back1: ENTITY unb2_board_lib.unb2_board_10gbe -- Upper Back lines u_tr_10GbE_back1: ENTITY unb2_board_lib.unb2_board_10gbe -- Upper Back lines
-- GENERIC MAP ( GENERIC MAP (
-- g_technology => g_technology, g_technology => g_technology,
-- g_sim => g_sim, g_sim => g_sim,
-- g_sim_level => 1, g_sim_level => 1,
-- g_nof_macs => g_nof_streams_back1, g_nof_macs => g_nof_streams_back1,
-- g_tx_fifo_fill => c_def_10GbE_block_size, g_tx_fifo_fill => c_def_10GbE_block_size,
-- g_tx_fifo_size => c_def_10GbE_block_size*2 g_tx_fifo_size => c_def_10GbE_block_size*2
-- ) )
-- PORT MAP ( PORT MAP (
-- tr_ref_clk => SB_CLK, tr_ref_clk => SB_CLK,
-- mm_rst => mm_rst, mm_rst => mm_rst,
-- mm_clk => mm_clk, mm_clk => mm_clk,
-- reg_mac_mosi => reg_tr_10GbE_back1_mosi, reg_mac_mosi => reg_tr_10GbE_back1_mosi,
-- reg_mac_miso => reg_tr_10GbE_back1_miso, reg_mac_miso => reg_tr_10GbE_back1_miso,
-- dp_rst => dp_rst, dp_rst => dp_rst,
-- dp_clk => dp_clk, dp_clk => dp_clk,
--
-- src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring), src_out_arr => dp_offload_rx_snk_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
-- src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring), src_in_arr => dp_offload_rx_snk_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
-- snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring), snk_out_arr => dp_offload_tx_src_in_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
-- snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring), snk_in_arr => dp_offload_tx_src_out_arr(g_nof_streams-1 DOWNTO g_nof_streams_back0+g_nof_streams_qsfp+g_nof_streams_ring),
--
-- serial_tx_arr => i_serial_10G_tx_back1_arr, serial_tx_arr => i_serial_10G_tx_back1_arr,
-- serial_rx_arr => i_serial_10G_rx_back1_arr serial_rx_arr => i_serial_10G_rx_back1_arr
-- ); );
...@@ -881,18 +881,18 @@ BEGIN ...@@ -881,18 +881,18 @@ BEGIN
END GENERATE; END GENERATE;
i_QSFP_RX(0) <= QSFP_0_RX; i_QSFP_RX(0) <= QSFP_0_RX;
-- i_QSFP_RX(1) <= QSFP_1_RX; i_QSFP_RX(1) <= QSFP_1_RX;
-- i_QSFP_RX(2) <= QSFP_2_RX; i_QSFP_RX(2) <= QSFP_2_RX;
-- i_QSFP_RX(3) <= QSFP_3_RX; i_QSFP_RX(3) <= QSFP_3_RX;
-- i_QSFP_RX(4) <= QSFP_4_RX; i_QSFP_RX(4) <= QSFP_4_RX;
-- i_QSFP_RX(5) <= QSFP_5_RX; i_QSFP_RX(5) <= QSFP_5_RX;
QSFP_0_TX <= i_QSFP_TX(0); QSFP_0_TX <= i_QSFP_TX(0);
-- QSFP_1_TX <= i_QSFP_TX(1); QSFP_1_TX <= i_QSFP_TX(1);
-- QSFP_2_TX <= i_QSFP_TX(2); QSFP_2_TX <= i_QSFP_TX(2);
-- QSFP_3_TX <= i_QSFP_TX(3); QSFP_3_TX <= i_QSFP_TX(3);
-- QSFP_4_TX <= i_QSFP_TX(4); QSFP_4_TX <= i_QSFP_TX(4);
-- QSFP_5_TX <= i_QSFP_TX(5); QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : ENTITY unb2_board_lib.unb2_board_front_io u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
GENERIC MAP ( GENERIC MAP (
...@@ -933,34 +933,34 @@ BEGIN ...@@ -933,34 +933,34 @@ BEGIN
); );
-- gen_back0_wires: FOR i IN 0 TO g_nof_streams_back0-1 GENERATE gen_back0_wires: FOR i IN 0 TO g_nof_streams_back0-1 GENERATE
-- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i); serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
-- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i); i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
-- END GENERATE; END GENERATE;
-- gen_back1_wires: FOR i IN 0 TO g_nof_streams_back1-1 GENERATE gen_back1_wires: FOR i IN 0 TO g_nof_streams_back1-1 GENERATE
-- serial_10G_tx_back_arr(i+g_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i); serial_10G_tx_back_arr(i+g_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
-- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+g_nof_streams_back0); i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+g_nof_streams_back0);
-- END GENERATE; END GENERATE;
--
-- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
-- GENERIC MAP ( GENERIC MAP (
-- g_nof_back_bus => g_nof_back_bus g_nof_back_bus => g_nof_back_bus
-- ) )
-- PORT MAP ( PORT MAP (
-- serial_tx_arr => serial_10G_tx_back_arr, serial_tx_arr => serial_10G_tx_back_arr,
-- serial_rx_arr => serial_10G_rx_back_arr, serial_rx_arr => serial_10G_rx_back_arr,
--
-- -- Serial I/O -- Serial I/O
-- -- back transceivers -- back transceivers
-- BCK_RX(0) => BCK_RX(g_nof_streams_back0-1 downto 0), BCK_RX(0) => BCK_RX(g_nof_streams_back0-1 downto 0),
-- BCK_TX(0) => BCK_TX(g_nof_streams_back0-1 downto 0), BCK_TX(0) => BCK_TX(g_nof_streams_back0-1 downto 0),
-- BCK_RX(1) => BCK_RX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0), BCK_RX(1) => BCK_RX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0),
-- BCK_TX(1) => BCK_TX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0), BCK_TX(1) => BCK_TX(g_nof_streams_back0+g_nof_streams_back1-1 downto g_nof_streams_back0),
--
-- BCK_SDA => BCK_SDA, BCK_SDA => BCK_SDA,
-- BCK_SCL => BCK_SCL, BCK_SCL => BCK_SCL,
-- BCK_ERR => BCK_ERR BCK_ERR => BCK_ERR
-- ); );
......
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