tb_tb_node_apertif_unb1_correlator_processing_output.vhd

applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg

@@ -18,11 +18,15 @@ synth_files =
     
 test_bench_files =
     tb/vhdl/tb_node_apertif_unb1_correlator_processing.vhd
-    tb/vhdl/tb_node_apertif_unb1_correlator_processing_output.vhd
     tb/vhdl/tb_tb_node_apertif_unb1_correlator_processing.vhd
+    tb/vhdl/tb_node_apertif_unb1_correlator_processing_output.vhd
+    tb/vhdl/tb_tb_node_apertif_unb1_correlator_processing_output.vhd
+    tb/vhdl/tb_apertif_unb1_correlator_nodes.vhd
 
 regression_test_vhdl = 
     tb/vhdl/tb_tb_node_apertif_unb1_correlator_processing.vhd
+    tb/vhdl/tb_tb_node_apertif_unb1_correlator_processing_output.vhd
+    tb/vhdl/tb_apertif_unb1_correlator_nodes.vhd
     
 [modelsim_project_file]
 modelsim_copy_files =