Renamed req_burst_cycles into burst_wr_cnt.

libraries/io/ddr/src/vhdl/io_ddr_driver.vhd

@@ -25,7 +25,7 @@
 --   Write or read a block of data to or from DDR memory. The data width is set
 --   by the DDR controller data width given by RESIZE_DDR_CTLR_DATA() and eg.
 --   256 bits for DDR3 with 64 bit DQ data. The block of data is located from
---   dvr_start_addr to dvr_end_addr.
+--   dvr_start_address to dvr_end_address.
 --   The io_ddr_driver takes care that the access is done in a number of bursts.
 --   The write burst size depends on the maximum burst size, the remaining
 --   block size and on the number of words available in the (external) FIFO as
@@ -78,21 +78,21 @@ ARCHITECTURE str OF io_ddr_driver IS
                                                 -- post a request for a too large burst size, which could cause the wr_burst state 
                                                 -- to be two valid words short.
 
-  SIGNAL req_burst_cycles       : STD_LOGIC_VECTOR(g_tech_ddr.maxburstsize_w-1 DOWNTO 0);
-  SIGNAL nxt_req_burst_cycles   : STD_LOGIC_VECTOR(g_tech_ddr.maxburstsize_w-1 DOWNTO 0);
-
   TYPE t_state_enum IS (s_init, s_idle, s_wait1, s_wait2, s_wait3, s_rd_request, s_wr_request, s_wr_burst);
 
   SIGNAL state                  : t_state_enum;
   SIGNAL nxt_state              : t_state_enum; 
   SIGNAL prev_state             : t_state_enum; 
 
-  SIGNAL wr_burst_size          : NATURAL;
-  SIGNAL rd_burst_size          : NATURAL;
+  SIGNAL wr_burst_size          : NATURAL RANGE 0 TO 2**g_tech_ddr.maxburstsize_w-1;
+  SIGNAL rd_burst_size          : NATURAL RANGE 0 TO 2**g_tech_ddr.maxburstsize_w-1;
 
   SIGNAL nxt_wr_burst_size      : NATURAL;
   SIGNAL nxt_rd_burst_size      : NATURAL;
 
+  SIGNAL burst_wr_cnt           : STD_LOGIC_VECTOR(g_tech_ddr.maxburstsize_w-1 DOWNTO 0);  -- count down from wr_burst_size to 0
+  SIGNAL nxt_burst_wr_cnt       : STD_LOGIC_VECTOR(g_tech_ddr.maxburstsize_w-1 DOWNTO 0);
+
   SIGNAL i_dvr_done             : STD_LOGIC;
   SIGNAL nxt_dvr_done           : STD_LOGIC;
 
@@ -113,7 +113,7 @@ BEGIN
   BEGIN
     IF rst='1' THEN
       state                <= s_init;
-      req_burst_cycles     <= (OTHERS => '0');
+      burst_wr_cnt         <= (OTHERS => '0');
       i_dvr_done           <= '0';
       cur_address          <= (OTHERS=>'0');
       wr_burst_size        <= 0;
@@ -123,7 +123,7 @@ BEGIN
       prev_state           <= s_idle;
     ELSIF rising_edge(clk) THEN
       state                <= nxt_state;
-      req_burst_cycles     <= nxt_req_burst_cycles;
+      burst_wr_cnt         <= nxt_burst_wr_cnt;
       i_dvr_done           <= nxt_dvr_done;
       cur_address          <= nxt_cur_address;
       wr_burst_size        <= nxt_wr_burst_size;
@@ -143,7 +143,7 @@ BEGIN
   p_wr_burst_size : PROCESS (reg_addresses_rem, reg_wr_fifo_usedw)
     VARIABLE v_burst_size : POSITIVE;
   BEGIN 
-    -- Write burst size at least 1 and if more then set to the smallest of g_tech_ddr.maxburstsize, addresses_rem and wr_fifo_usedw
+    -- Write burst size is at least 1 and if more then set to the smallest of g_tech_ddr.maxburstsize, addresses_rem and wr_fifo_usedw
     IF UNSIGNED(reg_wr_fifo_usedw)>c_margin AND UNSIGNED(reg_addresses_rem)>c_margin THEN 
       v_burst_size := g_tech_ddr.maxburstsize+c_margin;
       IF v_burst_size > UNSIGNED(reg_addresses_rem) THEN v_burst_size := TO_UINT(reg_addresses_rem); END IF;
@@ -172,7 +172,7 @@ BEGIN
   rd_src_out.data <= RESIZE_DP_DATA(ctlr_miso.rddata);
   
   p_state : PROCESS(prev_state, state, ctlr_init_done,
-                    dvr_en, dvr_wr_not_rd, i_dvr_done, ctlr_miso, req_burst_cycles, wr_snk_in, rd_src_in, 
+                    dvr_en, dvr_wr_not_rd, i_dvr_done, ctlr_miso, burst_wr_cnt, wr_snk_in, rd_src_in, 
                     wr_fifo_usedw, wr_burst_size, rd_burst_size, reg_addresses_rem, dvr_start_address, cur_address)
   BEGIN  
     nxt_state              <= state;
@@ -185,7 +185,7 @@ BEGIN
     ctlr_mosi.burstsize    <= (OTHERS => '0');
     
     wr_snk_out.ready       <= '0';
-    nxt_req_burst_cycles   <= req_burst_cycles;    
+    nxt_burst_wr_cnt       <= burst_wr_cnt;    
     nxt_dvr_done           <= i_dvr_done;
     nxt_cur_address        <= cur_address;
 
@@ -194,14 +194,14 @@ BEGIN
       WHEN s_wr_burst => -- Performs the burst portion (word 2+)        
         ctlr_mosi.wr <= '1';        
         IF ctlr_miso.waitrequest_n = '1' THEN
-          nxt_req_burst_cycles  <= INCR_UVEC(req_burst_cycles, -1);
-          wr_snk_out.ready  <= '1'; -- wr side uses latency of 0, so wr_snk_out.ready<='1' acknowledges a successful write request.
-          IF UNSIGNED(req_burst_cycles) = 1 THEN -- Then we're in the last cycle of this burst sequence
-            nxt_state <= s_wr_request; -- We can only initiate a new burst through the wr_request state
+          nxt_burst_wr_cnt  <= INCR_UVEC(burst_wr_cnt, -1);
+          wr_snk_out.ready  <= '1';           -- wr side uses latency of 0, so wr_snk_out.ready<='1' acknowledges a successful write request.
+          IF UNSIGNED(burst_wr_cnt) = 1 THEN  -- check for the last cycle of this burst sequence
+            nxt_state <= s_wr_request;        -- initiate a new wr burst or goto idle via the wr_request state
           END IF;
         END IF;            
 
-      WHEN s_wr_request => -- Performs 1 write or read and goes into s_wr_burst when requested write words >1         
+      WHEN s_wr_request =>  -- Performs 1 write access and goes into s_wr_burst when requested write words >1       
         nxt_state <= s_wait3; 
         IF UNSIGNED(reg_addresses_rem) = 0 THEN -- end address reached
           nxt_dvr_done  <= '1';              
@@ -215,8 +215,8 @@ BEGIN
             ctlr_mosi.burstsize  <= TO_DDR_CTLR_BURSTSIZE(wr_burst_size);  -- burstsize >= 1
             IF wr_burst_size > 1 THEN
               -- Perform any remaining writes in a burst
-              nxt_state            <= s_wr_burst;
-              nxt_req_burst_cycles <= TO_DDR_CTLR_BURSTSIZE(wr_burst_size-1); -- first burst wr cycle is done here, the rest are done in s_wr_burst
+              nxt_state        <= s_wr_burst;
+              nxt_burst_wr_cnt <= TO_DDR_CTLR_BURSTSIZE(wr_burst_size-1); -- first burst wr cycle is done here, the rest are done in s_wr_burst
             END IF; -- ELSE: there is only 1 word, so no need for remaining burst   
             nxt_cur_address   <= INCR_UVEC(cur_address, wr_burst_size);
           END IF;