changed transceiver_pll_10g GX output driver from x1 to master clock

(MCGB) (x6/xN)

libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd

@@ -279,11 +279,12 @@ BEGIN
   -- ATX PLL
   u_ip_arria10_transceiver_pll_10g : ip_arria10_transceiver_pll_10g
   PORT MAP (
-    pll_powerdown => atx_pll_powerdown_arr(0),   -- only use reset controller 0 for ATX PLL power down, leave others not used
-    pll_refclk0   => tr_ref_clk_644,
-    tx_serial_clk => tx_serial_clk(0),
-    pll_locked    => atx_pll_locked,
-    pll_cal_busy  => atx_pll_cal_busy
+    pll_powerdown   => atx_pll_powerdown_arr(0),   -- only use reset controller 0 for ATX PLL power down, leave others not used
+    pll_refclk0     => tr_ref_clk_644,
+    pll_locked      => atx_pll_locked,
+    pll_cal_busy    => atx_pll_cal_busy,
+    mcgb_rst        => atx_pll_powerdown_arr(0),
+    mcgb_serial_clk => tx_serial_clk(0)
   );
     
 END str;

libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd

@@ -119,11 +119,12 @@ PACKAGE tech_10gbase_r_component_pkg IS
 
   COMPONENT ip_arria10_transceiver_pll_10g IS
   PORT (
-    pll_powerdown : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
-    pll_refclk0   : in  std_logic := '0'; --   pll_refclk0.clk
-    tx_serial_clk : out std_logic;        -- tx_serial_clk.clk
-    pll_locked    : out std_logic;        --    pll_locked.pll_locked
-    pll_cal_busy  : out std_logic         --  pll_cal_busy.pll_cal_busy
+    pll_powerdown   : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
+    pll_refclk0     : in  std_logic := '0'; --   pll_refclk0.clk
+    pll_locked      : out std_logic;        --    pll_locked.pll_locked
+    pll_cal_busy    : out std_logic;        --  pll_cal_busy.pll_cal_busy
+    mcgb_rst        : in  std_logic := '0';
+    mcgb_serial_clk : out std_logic         -- tx_serial_clk.clk
   );
   END COMPONENT;
 

libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g.qsys

@@ -45,6 +45,20 @@
  <parameter name="timeStamp" value="0" />
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
+ <interface
+   name="mcgb_rst"
+   internal="xcvr_atx_pll_a10_0.mcgb_rst"
+   type="conduit"
+   dir="end">
+  <port name="mcgb_rst" internal="mcgb_rst" />
+ </interface>
+ <interface
+   name="mcgb_serial_clk"
+   internal="xcvr_atx_pll_a10_0.mcgb_serial_clk"
+   type="hssi_serial_clock"
+   dir="start">
+  <port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
+ </interface>
  <interface
    name="pll_cal_busy"
    internal="xcvr_atx_pll_a10_0.pll_cal_busy"
@@ -73,13 +87,7 @@
    dir="end">
   <port name="pll_refclk0" internal="pll_refclk0" />
  </interface>
- <interface
-   name="tx_serial_clk"
-   internal="xcvr_atx_pll_a10_0.tx_serial_clk"
-   type="hssi_serial_clock"
-   dir="start">
-  <port name="tx_serial_clk" internal="tx_serial_clk" />
- </interface>
+ <interface name="tx_serial_clk" internal="xcvr_atx_pll_a10_0.tx_serial_clk" />
  <module
    name="xcvr_atx_pll_a10_0"
    kind="altera_xcvr_atx_pll_a10"
@@ -91,15 +99,15 @@
   <parameter name="device" value="10AX115U3F45I2LG" />
   <parameter name="device_family" value="Arria 10" />
   <parameter name="enable_16G_path" value="0" />
-  <parameter name="enable_8G_path" value="1" />
+  <parameter name="enable_8G_path" value="0" />
   <parameter name="enable_bonding_clks" value="0" />
   <parameter name="enable_cascade_out" value="0" />
   <parameter name="enable_debug_ports_parameters" value="0" />
   <parameter name="enable_fb_comp_bonding" value="0" />
   <parameter name="enable_fractional" value="0" />
-  <parameter name="enable_hfreq_clk" value="0" />
+  <parameter name="enable_hfreq_clk" value="1" />
   <parameter name="enable_hip_cal_done_port" value="0" />
-  <parameter name="enable_mcgb" value="0" />
+  <parameter name="enable_mcgb" value="1" />
   <parameter name="enable_mcgb_pcie_clksw" value="0" />
   <parameter name="enable_pcie_clk" value="0" />
   <parameter name="enable_pld_atx_cal_busy_port" value="1" />