Use stop toggling instead of severity failure to stop simulation, because...

Use stop toggling instead of severity failure to stop simulation, because otherwise the tb cannot be used as component in a multi-tb.

libraries/io/eth/tb/vhdl/tb_eth.vhd

@@ -264,8 +264,8 @@ BEGIN
 
   -- run 50 us
   
-  eth_clk <= NOT eth_clk AFTER eth_clk_period/2;  -- TSE reference clock
-  sys_clk <= NOT sys_clk AFTER sys_clk_period/2;  -- System clock
+  eth_clk <= NOT eth_clk OR tb_end AFTER eth_clk_period/2;  -- TSE reference clock
+  sys_clk <= NOT sys_clk OR tb_end AFTER sys_clk_period/2;  -- System clock
 
   mm_clk  <= sys_clk;
   st_clk  <= sys_clk;
@@ -569,8 +569,8 @@ BEGIN
       REPORT "Not all transmitted packets were received." SEVERITY ERROR;
     END IF;
     
-    -- Stop the simulation
-    ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+    WAIT FOR 10 us;
+    ASSERT FALSE REPORT "Simulation tb_eth finished." SEVERITY NOTE;
     WAIT;
   END PROCESS;
   

libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd

@@ -44,6 +44,7 @@ ARCHITECTURE tb OF tb_eth_IHL_to_20 IS
   CONSTANT clk_period : TIME := 5 ns;  -- 100 MHz
 
 
+  SIGNAL tb_end         : STD_LOGIC := '0';
   SIGNAL clk            : STD_LOGIC := '0';
   SIGNAL rst            : STD_LOGIC;
 
@@ -171,7 +172,7 @@ ARCHITECTURE tb OF tb_eth_IHL_to_20 IS
   
 BEGIN
 
-  clk <= NOT clk AFTER clk_period/2;
+  clk <= NOT clk OR tb_end AFTER clk_period/2;
   rst <= '1', '0' AFTER clk_period*7;
   
   
@@ -189,7 +190,9 @@ BEGIN
     END LOOP;
     
     wait for 1 ms;
-    ASSERT FALSE REPORT "ERROR: Processing was too long.  DUT is stuck" SEVERITY FAILURE;
+    IF tb_end='0' THEN
+      ASSERT FALSE REPORT "ERROR: Processing was too long. DUT is stuck" SEVERITY FAILURE;
+    END IF;
     WAIT;
   END PROCESS;
 
@@ -217,14 +220,13 @@ BEGIN
 
     FOR len_n in c_len_to_test'RANGE LOOP
       FOR IHL_n in c_IHL_to_test'RANGE LOOP
-        check_eth_frame (
-                         c_len_to_test(len_n),
-                         clk,src_out);
+        check_eth_frame (c_len_to_test(len_n), clk, src_out);
       END LOOP;
     END LOOP;
     
     WAIT for 1 us;
-    ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+    tb_end <= '1';
+    ASSERT FALSE REPORT "Simulation tb_eth_IHL_to_20 finished." SEVERITY NOTE;
     WAIT;
   END PROCESS;
 

libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd

@@ -362,7 +362,7 @@ BEGIN
   BEGIN
     WAIT UNTIL tb_end='1';
     WAIT FOR 10 us;
-    ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+    ASSERT FALSE REPORT "Simulation tb_eth_udp_offload finished." SEVERITY NOTE;
     WAIT;
   END PROCESS;