Improved description.

libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt

@@ -5,7 +5,7 @@ Contents:
 2) IP component
 3) Compilation, simulation and verification
 4) Synthesis
-
+5) Remarks
 
 
 1) Porting
@@ -18,23 +18,24 @@ the same parameter settings.
 
 The generated IP is not kept in SVN, only the Qsys source file:
 
-  ip_arria10_tse_sgmii_lvds.qsys
+  ip/ip_arria10_tse_sgmii_lvds.qsys
 
 Therefore first the IP needs to be generated using:
 
-  ./generate_ip.sh
+  ip/generate_ip.sh
   
 
 3) Compilation, simulation and verification
 
 The genrated IP also contains a msim_setup.tcl file that was used to manually create:
 
-  compile_ip.tcl
+  ip/compile_ip.tcl
+  
+This ip/compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
 
-This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
 The IP can be verified with the self checking test bench:
 
-  tb_ip_arria10_tse_sgmii_lvds.vhd
+  tb_ip_arria10_tse_sgmii_lvds_top.vhd
   
 This test bench is functionally identical to tb_ip_stratixiv_tse_sgmii_lvds.vhd, but instead it instantiates the ip_arria10_tse_sgmii_lvds.vhd
 component as DUT.
@@ -44,24 +45,26 @@ component as DUT.
 
 No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
 
-  generated/ip_arria10_tse_sgmii_lvds.qip
+  ip/generated/ip_arria10_tse_sgmii_lvds.qip
 
-is included in the hdllib.cfg and contains what is needed to synthesize the IP.
+is included in the ip/hdllib.cfg and contains what is needed to synthesize the IP.
 
 
-5) Issues
+5) Remarks
 
 a) Generated ip_arria10_tse_sgmii_lvds.vhd uses IP specific library ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
      
   The generated ip_arria10_tse_sgmii_lvds.vhd uses library ip_arria10_tse_sgmii_lvds_altera_eth_tse_140. This library needs to be vmap-ed
   in every design that uses this IP. Therefore to make this library known created it in the ./ip directory with its own hdllib.cfg. The 
-  hdllib.cfg defines the IP library:
+  ip/hdllib.cfg defines the IP library:
   
-    hdl_lib_name = ip_arria10_tse_sgmii_lvds               
-    hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_lib
+    hdl_lib_name = ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
+    hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
    
   The ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library name is IP specific. The tech_tse/ library should not need to know about it, so
-  therefore use a wrapper in ip_arria10_tse_sgmii_lvds_lib that merely instantiates the IP.
+  therefore use the ip_arria10_tse_sgmii_lvds_top.vhd wrapper in ip_arria10_tse_sgmii_lvds_lib that merely instantiates the IP. The
+  ip_arria10_tse_sgmii_lvds_top.vhd wrapper makes the IP accessible via ip_arria10_tse_sgmii_lvds_lib, to avoid that the IP specific library
+  needs to be used at the technology independent level.
   
   An alternative would be to directly instantiate the generated IP ip_arria10_tse_sgmii_lvds.vhd in tech_tse_arria10.vhd, but then the
   ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 also needs to be vmap-ped for the tech_tse library. This vmap could be done with a map_ip.tcl
@@ -75,5 +78,5 @@ a) Generated ip_arria10_tse_sgmii_lvds.vhd uses IP specific library ip_arria10_t
 b) Generated IP uses several more libraries
 
   The generated IP uses several more libraries. Just as the ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library these other libraries are
-  all mapped to ./work in compile_ip.tcl.
+  all mapped to ./work in ip/compile_ip.tcl.
   
\ No newline at end of file