Renamed dp_stimuli_st.vhd into dp_stream_stimuli.vhd.

Renamed dp_verify_st.vhd into dp_stream_verify.vhd.

libraries/base/dp/hdllib.cfg

@@ -124,8 +124,8 @@ test_bench_files =
     $UNB/Firmware/modules/dp/tb/vhdl/tb_dp_pkg.vhd
     
     $UNB/Firmware/modules/dp/tb/vhdl/dp_phy_link.vhd
-    tb/vhdl/dp_stimuli_st.vhd
-    tb/vhdl/dp_verify_st.vhd
+    tb/vhdl/dp_stream_stimuli.vhd
+    tb/vhdl/dp_stream_verify.vhd
     
     $UNB/Firmware/modules/dp/tb/vhdl/tb_dp_block_gen.vhd
     $UNB/Firmware/modules/dp/tb/vhdl/tb_dp_bsn_align.vhd

libraries/base/dp/tb/vhdl/dp_stimuli_st.vhd → libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd

@@ -20,7 +20,7 @@
 -------------------------------------------------------------------------------
 
 -- Purpose:
--- . The dp_stimuli_st generates as stream of packets with counter data.
+-- . The dp_stream_stimuli generates as stream of packets with counter data.
 -- Description:
 --
 -- Usage:
@@ -37,7 +37,7 @@ USE work.dp_stream_pkg.ALL;
 USE work.tb_dp_pkg.ALL;
 
 
-ENTITY dp_stimuli_st IS
+ENTITY dp_stream_stimuli IS
   GENERIC (
     g_instance_nr    : NATURAL := 0;
     -- flow control
@@ -69,12 +69,12 @@ ENTITY dp_stimuli_st IS
     -- End of stimuli
     last_snk_in       : OUT t_dp_sosi;   -- expected verify_snk_in after end of stimuli 
     last_snk_in_evt   : OUT STD_LOGIC;   -- trigger verify to verify the last_snk_in 
-    tb_end            : OUT STD_LOGIC    -- signal end of tb as far as this dp_stimuli_st is concerned
+    tb_end            : OUT STD_LOGIC    -- signal end of tb as far as this dp_stream_stimuli is concerned
   );
-END dp_stimuli_st;
+END dp_stream_stimuli;
 
 
-ARCHITECTURE str OF dp_stimuli_st IS
+ARCHITECTURE str OF dp_stream_stimuli IS
   
   SIGNAL random          : STD_LOGIC_VECTOR(g_random_w-1 DOWNTO 0) := TO_UVEC(g_instance_nr, g_random_w);  -- use different initialization to have different random sequences per stream
   SIGNAL pulse           : STD_LOGIC;

libraries/base/dp/tb/vhdl/dp_verify_st.vhd → libraries/base/dp/tb/vhdl/dp_stream_verify.vhd

@@ -20,7 +20,7 @@
 -------------------------------------------------------------------------------
 
 -- Purpose:
--- . The dp_verify_st verifies the stream of packets with counter data that
+-- . The dp_stream_verify verifies the stream of packets with counter data that
 --   are generated by dp_stimuli_st.
 -- Description:
 --   The component can verify a stream:
@@ -48,7 +48,7 @@ USE work.dp_stream_pkg.ALL;
 USE work.tb_dp_pkg.ALL;
 
 
-ENTITY dp_verify_st IS
+ENTITY dp_stream_verify IS
   GENERIC (
     g_instance_nr         : NATURAL := 0;
     -- flow control
@@ -80,10 +80,10 @@ ENTITY dp_verify_st IS
     expected_snk_in            : IN  t_dp_sosi;          -- expected snk_in at verify_expected_snk_in_evt
     verify_expected_snk_in_evt : IN  t_dp_sosi_sl   -- trigger to verify the expected_snk_in 
   );
-END dp_verify_st;
+END dp_stream_verify;
 
 
-ARCHITECTURE tb OF dp_verify_st IS
+ARCHITECTURE tb OF dp_stream_verify IS
 
   CONSTANT c_rl                       : NATURAL := 1;
   CONSTANT c_no_dut                   : BOOLEAN:= TRUE;

libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd

@@ -138,7 +138,7 @@ ARCHITECTURE tb OF tb_dp_example_no_dut IS
 
   CONSTANT c_no_dut                   : BOOLEAN:= TRUE;
 
-  -- dp_stimuli_st
+  -- dp_stream_stimuli
   CONSTANT c_stimuli_pulse_active     : NATURAL := 1;
   CONSTANT c_stimuli_pulse_period     : NATURAL := 2;
   
@@ -147,7 +147,7 @@ ARCHITECTURE tb OF tb_dp_example_no_dut IS
   CONSTANT c_err_init                 : NATURAL := 247;
   CONSTANT c_channel_init             : INTEGER := 5;  -- fixed
   
-  -- dp_verify_st
+  -- dp_stream_verify
   CONSTANT c_verify_pulse_active      : NATURAL := 1;
   CONSTANT c_verify_pulse_period      : NATURAL := 2;
   
@@ -194,7 +194,7 @@ BEGIN
   -- DATA GENERATION
   ------------------------------------------------------------------------------
   
-  u_dp_stimuli_st : ENTITY work.dp_stimuli_st
+  u_dp_stream_stimuli : ENTITY work.dp_stream_stimuli
   GENERIC MAP (
     g_instance_nr    => 0,                        -- only one stream so choose index 0
     -- flow control
@@ -226,7 +226,7 @@ BEGIN
     -- End of stimuli
     last_snk_in         => last_snk_in,      -- expected verify_snk_in after end of stimuli 
     last_snk_in_evt     => last_snk_in_evt,  -- trigger verify to verify the last_snk_in 
-    tb_end              => tb_end            -- signal end of tb as far as this dp_stimuli_st is concerned
+    tb_end              => tb_end            -- signal end of tb as far as this dp_stream_stimuli is concerned
   );
   
   
@@ -261,7 +261,7 @@ BEGIN
   verify_last_snk_in_evt.channel <= '0';
   verify_last_snk_in_evt.err     <= '0';
   
-  u_dp_verify_st : ENTITY work.dp_verify_st
+  u_dp_stream_verify : ENTITY work.dp_stream_verify
   GENERIC MAP (
     g_instance_nr    => 0,                        -- only one stream so choose index 0
     -- flow control