synced system info to fix address error (L2SDP-148)

applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys

@@ -4893,47 +4893,6 @@
 </componentDefinition>]]></parameter>
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
-        <interface>
-            <name>clk</name>
-            <type>clock</type>
-            <isStart>true</isStart>
-            <ports>
-                <port>
-                    <name>clk_out</name>
-                    <role>clk</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedDirectClock</key>
-                        <value>clk_in</value>
-                    </entry>
-                    <entry>
-                        <key>clockRate</key>
-                        <value>100000000</value>
-                    </entry>
-                    <entry>
-                        <key>clockRateKnown</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>externallyDriven</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>ptfSchematicName</key>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
         <interface>
             <name>clk_in</name>
             <type>clock</type>
@@ -5006,6 +4965,47 @@
                 </parameterValueMap>
             </parameters>
         </interface>
+        <interface>
+            <name>clk</name>
+            <type>clock</type>
+            <isStart>true</isStart>
+            <ports>
+                <port>
+                    <name>clk_out</name>
+                    <role>clk</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedDirectClock</key>
+                        <value>clk_in</value>
+                    </entry>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>100000000</value>
+                    </entry>
+                    <entry>
+                        <key>clockRateKnown</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
         <interface>
             <name>clk_reset</name>
             <type>reset</type>
@@ -18379,7 +18379,7 @@
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>