Added adjustable pipelining that takes into account the g_align_out setting.

This all in order to make the g_use_ctrl generic work fine. 
It works fine now! 

libraries/base/dp/src/vhdl/dp_deinterleave.vhd

@@ -54,6 +54,12 @@ END dp_deinterleave;
 
 ARCHITECTURE wrap OF dp_deinterleave IS
 
+  -- Naturals that define the amount of pipelining for the control signals. 
+  -- Different pipeline stages when g_align_out = FALSE. When g_align_out = TRUE, every pipeline gets the same amount of buffering. 
+  CONSTANT c_nof_pipelines_decre  : t_nat_natural_arr(0 TO g_nof_out-1) := array_init(g_block_size, g_nof_out, g_block_size); 
+  CONSTANT c_nof_pipelines_fixed  : t_nat_natural_arr(0 TO g_nof_out-1) := (OTHERS => g_nof_out*g_block_size); 
+  CONSTANT c_nof_pipelines        : t_nat_natural_arr(0 TO g_nof_out-1) := sel_a_b(g_align_out, c_nof_pipelines_fixed, c_nof_pipelines_decre); 
+
   CONSTANT c_complex_w  : NATURAL := g_dat_w/2;
 
   -- Arrays flattened into SLVs
@@ -156,7 +162,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- Forward and align the input Sync, BSN, SOP and EOP with the outputs
   -----------------------------------------------------------------------------
-  gen_ctrl : if g_use_ctrl=TRUE GENERATE
+  gen_ctrl : IF g_use_ctrl=TRUE GENERATE
     gen_out_pipes: FOR i IN 0 TO g_nof_out-1 GENERATE
       -----------------------------------------------------------------------------
       -- Before forwarding the remaining (ctrl) signals to the outputs, they also 
@@ -168,9 +174,10 @@ BEGIN
       -- *this excludes eop as that was the reason for delaying the other inputs
       --  by g_block_size cycles in the first place.
       -----------------------------------------------------------------------------
+      
       u_pipe_sync : ENTITY common_lib.common_pipeline
       GENERIC MAP (
-        g_pipeline  => g_block_size + i*g_block_size,
+        g_pipeline  => c_nof_pipelines(i), 
         g_in_dat_w  => 1,
         g_out_dat_w => 1
       )
@@ -183,7 +190,7 @@ BEGIN
 
       u_pipe_bsn : ENTITY common_lib.common_pipeline
       GENERIC MAP (
-        g_pipeline  => g_block_size + i*g_block_size,
+        g_pipeline  => c_nof_pipelines(i), 
         g_in_dat_w  => c_dp_stream_bsn_w,
         g_out_dat_w => c_dp_stream_bsn_w
       )
@@ -196,7 +203,7 @@ BEGIN
 
       u_pipe_sop : ENTITY common_lib.common_pipeline
       GENERIC MAP (
-        g_pipeline  => g_block_size + i*g_block_size,
+        g_pipeline  => c_nof_pipelines(i), 
         g_in_dat_w  => 1,
         g_out_dat_w => 1
       )
@@ -207,9 +214,10 @@ BEGIN
         sl(out_dat) => src_out_arr(i).sop
       );
 
+      -- EOP should be one earlier then the other signals
       u_pipe_eop : ENTITY common_lib.common_pipeline
       GENERIC MAP (
-        g_pipeline  => i*g_block_size,
+        g_pipeline  => c_nof_pipelines(i)-1, 
         g_in_dat_w  => 1,
         g_out_dat_w => 1
       )
@@ -222,7 +230,7 @@ BEGIN
 
       u_pipe_err : ENTITY common_lib.common_pipeline
       GENERIC MAP (
-        g_pipeline  => g_block_size + i*g_block_size,
+        g_pipeline  => c_nof_pipelines(i), 
         g_in_dat_w  => c_dp_stream_error_w,
         g_out_dat_w => c_dp_stream_error_w
       )
@@ -235,7 +243,7 @@ BEGIN
 
       u_pipe_empty : ENTITY common_lib.common_pipeline
       GENERIC MAP (
-        g_pipeline  => g_block_size + i*g_block_size,
+        g_pipeline  => c_nof_pipelines(i), 
         g_in_dat_w  => c_dp_stream_empty_w,
         g_out_dat_w => c_dp_stream_empty_w
       )
@@ -248,7 +256,7 @@ BEGIN
 
       u_pipe_channel : ENTITY common_lib.common_pipeline
       GENERIC MAP (
-        g_pipeline  => g_block_size + i*g_block_size,
+        g_pipeline  => c_nof_pipelines(i), 
         g_in_dat_w  => c_dp_stream_channel_w,
         g_out_dat_w => c_dp_stream_channel_w
       )