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Commit 618e1530 authored by Pepping's avatar Pepping
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- Fixed all errors due to to copy. Addapted to RadioHDL envuironment

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applications/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+ 5
− 37
View file @ 618e1530
...@@ -24,20 +24,17 @@ USE IEEE.STD_LOGIC_1164.ALL; ...@@ -24,20 +24,17 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL; USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL; USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL; USE common_lib.common_network_total_header_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL; USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL; USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL; USE mm_lib.mm_file_unb_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
--USE tse_lib.tse_pkg.ALL;
--USE tse_lib.tb_tse_pkg.ALL;
USE eth_lib.eth_pkg.ALL; USE eth_lib.eth_pkg.ALL;
USE technology_lib.technology_pkg.ALL; USE technology_lib.technology_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL; USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL; USE tech_tse_lib.tb_tech_tse_pkg.ALL;
--USE tse_lib.eth_layers_pkg.ALL;
USE bf_lib.bf_pkg.ALL; USE bf_lib.bf_pkg.ALL;
ENTITY mmm_fn_bf IS ENTITY mmm_fn_bf IS
...@@ -281,35 +278,6 @@ BEGIN ...@@ -281,35 +278,6 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
--p_eth_setup : PROCESS
--BEGIN
-- mm_bus_switch <= '1';
--
-- eth1g_tse_mosi.wr <= '0';
-- eth1g_tse_mosi.rd <= '0';
-- WAIT FOR 400 ns;
-- WAIT UNTIL rising_edge(i_mm_clk);
-- proc_tse_setup(FALSE, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tse_tx_ready_latency, c_dut_src_mac, eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
--
-- -- Enable RX
-- proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi); -- control rx en
-- mm_bus_switch <= '0';
--
-- WAIT;
--END PROCESS;
--
--p_switch : PROCESS(mm_bus_switch, eth1g_reg_proc_mosi, i_eth1g_reg_mosi)
--BEGIN
-- IF mm_bus_switch = '1' THEN
-- eth1g_reg_mosi <= eth1g_reg_proc_mosi;
-- ELSE
-- eth1g_reg_mosi <= i_eth1g_reg_mosi;
-- END IF;
--END PROCESS;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get -- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns -- the simulation time in ns
...@@ -326,7 +294,7 @@ BEGIN ...@@ -326,7 +294,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
gen_sopc : IF g_sim = FALSE GENERATE gen_sopc : IF g_sim = FALSE GENERATE
u_sopc : ENTITY work.sopc_fn_bf u_sopc : ENTITY work.sopc_unb1_fn_bf
PORT MAP ( PORT MAP (
-- 1) global signals: -- 1) global signals:
clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
......
applications/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
+ 7
− 6
View file @ 618e1530
...@@ -19,18 +19,19 @@ ...@@ -19,18 +19,19 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib, diag_lib, bf_lib, tse_lib; LIBRARY IEEE, common_lib, dp_lib, diag_lib, eth_lib, tech_tse_lib, bf_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL; USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL; USE diag_lib.diag_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE bf_lib.ALL; USE bf_lib.ALL;
USE bf_lib.bf_pkg.ALL; USE bf_lib.bf_pkg.ALL;
USE tse_lib.tse_pkg.ALL;
USE tse_lib.eth_layers_pkg.ALL;
USE tse_lib.eth_pkg.ALL;
ENTITY node_fn_bf IS ENTITY node_fn_bf IS
GENERIC( GENERIC(
...@@ -184,11 +185,11 @@ BEGIN ...@@ -184,11 +185,11 @@ BEGIN
u_dp_offload : ENTITY dp_lib.dp_offload_tx u_dp_offload : ENTITY dp_lib.dp_offload_tx
GENERIC MAP ( GENERIC MAP (
g_nof_streams => g_bf.nof_bf_units, g_nof_streams => g_bf.nof_bf_units,
g_data_w => c_tse_data_w, g_data_w => c_eth_data_w,
g_block_size => g_bf.nof_weights, -- = 256 g_block_size => g_bf.nof_weights, -- = 256
g_block_nof_sel_words => 20, g_block_nof_sel_words => 20,
g_nof_words_per_pkt => 360, g_nof_words_per_pkt => 360,
g_hdr_nof_words => c_eth_total_header_nof_words, g_hdr_nof_words => c_network_total_header_32b_nof_words,
g_use_complex => TRUE, g_use_complex => TRUE,
g_use_input_fifo => TRUE, g_use_input_fifo => TRUE,
g_use_output_fifo => TRUE g_use_output_fifo => TRUE
......
applications/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
+ 20
− 18
View file @ 618e1530
...@@ -19,17 +19,19 @@ ...@@ -19,17 +19,19 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb_common_lib, dp_lib, tse_lib, bf_lib; LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, bf_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL; USE common_lib.common_mem_pkg.ALL;
USE unb_common_lib.unb_common_pkg.ALL; USE common_lib.common_network_layers_pkg.ALL;
USE unb_common_lib.unb_peripherals_pkg.ALL; USE common_lib.common_network_total_header_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL;
USE tse_lib.eth_layers_pkg.ALL; USE eth_lib.eth_pkg.ALL;
USE tse_lib.tse_pkg.ALL; USE tech_tse_lib.tech_tse_pkg.ALL;
USE tse_lib.eth_pkg.ALL; USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE bf_lib.bf_pkg.ALL; USE bf_lib.bf_pkg.ALL;
ENTITY unb1_fn_bf IS ENTITY unb1_fn_bf IS
...@@ -53,9 +55,9 @@ ENTITY unb1_fn_bf IS ...@@ -53,9 +55,9 @@ ENTITY unb1_fn_bf IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others -- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb_aux.version_w-1 DOWNTO 0); VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb_aux.id_w-1 DOWNTO 0); ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb_aux.testio_w-1 DOWNTO 0); TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors -- I2C Interface to Sensors
sens_sc : INOUT STD_LOGIC; sens_sc : INOUT STD_LOGIC;
...@@ -73,8 +75,8 @@ ARCHITECTURE str OF unb1_fn_bf IS ...@@ -73,8 +75,8 @@ ARCHITECTURE str OF unb1_fn_bf IS
CONSTANT c_bf_offload : BOOLEAN := FALSE; -- Offload BF out(0) datapath to 1GbE UDP TX port CONSTANT c_bf_offload : BOOLEAN := FALSE; -- Offload BF out(0) datapath to 1GbE UDP TX port
CONSTANT c_use_phy : t_c_unb_use_phy := (1, 0, 0, 0, 0, 0, 0, 1); CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 0, 0, 0, 1);
CONSTANT c_fw_version : t_unb_fw_version := (2, 3); -- firmware version x.y CONSTANT c_fw_version : t_unb1_board_fw_version := (2, 3); -- firmware version x.y
CONSTANT c_nof_streams : NATURAL := c_eth_nof_udp_ports; CONSTANT c_nof_streams : NATURAL := c_eth_nof_udp_ports;
CONSTANT c_weights_write_only : BOOLEAN := TRUE; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port. CONSTANT c_weights_write_only : BOOLEAN := TRUE; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
...@@ -84,8 +86,8 @@ ARCHITECTURE str OF unb1_fn_bf IS ...@@ -84,8 +86,8 @@ ARCHITECTURE str OF unb1_fn_bf IS
CONSTANT c_block_gen_file_prefix : STRING := sel_a_b(g_sim, "../", "") & "../../../../../modules/Lofar/diag/src/data/bf_in_data"; CONSTANT c_block_gen_file_prefix : STRING := sel_a_b(g_sim, "../", "") & "../../../../../modules/Lofar/diag/src/data/bf_in_data";
-- BF offload -- BF offload
CONSTANT c_hdr_nof_words : NATURAL := c_eth_total_header_nof_words; CONSTANT c_hdr_nof_words : NATURAL := c_network_total_header_32b_nof_words;
CONSTANT c_dp_ram_mm_nof_words : NATURAL := c_hdr_nof_words * (c_tse_data_w/c_word_w); CONSTANT c_dp_ram_mm_nof_words : NATURAL := c_hdr_nof_words * (c_eth_data_w/c_word_w);
CONSTANT c_dp_ram_mm_adr_w : NATURAL := ceil_log2(c_dp_ram_mm_nof_words); CONSTANT c_dp_ram_mm_adr_w : NATURAL := ceil_log2(c_dp_ram_mm_nof_words);
-- System -- System
...@@ -131,7 +133,7 @@ ARCHITECTURE str OF unb1_fn_bf IS ...@@ -131,7 +133,7 @@ ARCHITECTURE str OF unb1_fn_bf IS
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
SIGNAL eth1g_ram_miso : t_mem_miso; SIGNAL eth1g_ram_miso : t_mem_miso;
SIGNAL eth1g_led : t_tse_led; SIGNAL eth1g_led : t_tech_tse_led;
-- eth1g UDP streaming ports -- eth1g UDP streaming ports
SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0); SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
...@@ -210,11 +212,11 @@ BEGIN ...@@ -210,11 +212,11 @@ BEGIN
mm_locked => mm_locked, mm_locked => mm_locked,
mm_rst => mm_rst, mm_rst => mm_rst,
dp_rst => st_rst, dp_rst => dp_rst,
dp_clk => st_clk, dp_clk => dp_clk,
dp_pps => OPEN, dp_pps => OPEN,
dp_rst_in => st_rst, dp_rst_in => dp_rst,
dp_clk_in => st_clk, dp_clk_in => dp_clk,
-- Toggle WDI -- Toggle WDI
pout_wdi => pout_wdi, pout_wdi => pout_wdi,
......
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