Added dp_verify_st.vhd.

libraries/base/dp/hdllib.cfg

@@ -125,6 +125,7 @@ test_bench_files =
     
     $UNB/Firmware/modules/dp/tb/vhdl/dp_phy_link.vhd
     tb/vhdl/dp_stimuli_st.vhd
+    tb/vhdl/dp_verify_st.vhd
     
     $UNB/Firmware/modules/dp/tb/vhdl/tb_dp_block_gen.vhd
     $UNB/Firmware/modules/dp/tb/vhdl/tb_dp_bsn_align.vhd

libraries/base/dp/tb/vhdl/dp_verify_st.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- . The dp_verify_st verifies the stream of packets with counter data that
+--   are generated by dp_stimuli_st.
+-- Description:
+--
+-- Usage:
+-- . See tb_dp_example_no_dut for usage example
+--
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+
+ENTITY dp_verify_st IS
+  GENERIC (
+    g_instance_nr    : NATURAL := 0;
+    -- flow control
+    g_random_w       : NATURAL := 14;                       -- use different random width for stimuli and for verify to have different random sequences
+    g_pulse_active   : NATURAL := 1;
+    g_pulse_period   : NATURAL := 2;
+    g_flow_control   : t_dp_flow_control_enum := e_active;  -- always active, random or pulse flow control
+    -- initializations
+    g_sync_period    : NATURAL := 10;
+    g_sync_offset    : NATURAL := 7;
+    -- specific
+    g_in_dat_w       : NATURAL := 32;
+    g_pkt_len        : NATURAL := 16;
+  );
+  PORT (
+    rst                      : IN  STD_LOGIC;
+    clk                      : IN  STD_LOGIC;
+  
+    -- Verify data
+    verify_snk_out           : OUT t_dp_siso;
+    verify_snk_in            : IN  t_dp_sosi;
+
+    -- End of stimuli
+    expected_verify_snk_in   : IN  t_dp_sosi;   -- expected verify_snk_in after end of stimuli 
+    verify_last              : IN  STD_LOGIC;   -- trigger verify to verify the expected_verify_snk_in 
+    tb_end                   : IN  STD_LOGIC    -- signal end of tb as far as this dp_stimuli_st is concerned
+  );
+END dp_verify_st;
+
+
+ARCHITECTURE tb OF dp_verify_st IS
+
+  CONSTANT c_rl                       : NATURAL := 1;
+  CONSTANT c_no_dut                   : BOOLEAN:= TRUE;
+  
+  CONSTANT c_data_max                 : UNSIGNED(g_in_dat_w-1 DOWNTO 0) := (OTHERS=>'1');
+  
+  SIGNAL tb_end                     : STD_LOGIC := '0';
+  SIGNAL clk                        : STD_LOGIC := '1';
+  SIGNAL rst                        : STD_LOGIC := '1';
+  SIGNAL sl1                        : STD_LOGIC := '1';
+  
+  SIGNAL random                     : STD_LOGIC_VECTOR(g_random_w-1 DOWNTO 0) := TO_UVEC(g_instance_nr, g_random_w);  -- use different initialization to have different random sequences per stream
+  SIGNAL pulse                      : STD_LOGIC;
+  SIGNAL pulse_en                   : STD_LOGIC := '1';
+  
+  SIGNAL prev_verify_snk_out        : t_dp_siso;
+  SIGNAL verify_snk_out             : t_dp_siso := c_dp_siso_rdy;
+  SIGNAL verify_snk_in              : t_dp_sosi;
+  SIGNAL verify_snk_in_data         : STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0);  -- used to hold valid data for verify at verify_last
+  SIGNAL verify_data                : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
+  SIGNAL prev_verify_snk_in         : t_dp_sosi;
+  
+  SIGNAL verify_hold_sop            : STD_LOGIC := '0';
+  SIGNAL verify_en_valid            : STD_LOGIC := '0';
+  SIGNAL verify_en_sop              : STD_LOGIC := '0';
+  SIGNAL verify_en_eop              : STD_LOGIC := '0';
+  
+  SIGNAL exp_size                   : NATURAL;
+  SIGNAL cnt_size                   : NATURAL;
+  
+BEGIN
+
+  ------------------------------------------------------------------------------
+  -- DATA VERIFICATION
+  ------------------------------------------------------------------------------
+  
+  random_1 <= func_common_random(random_1) WHEN rising_edge(clk);
+  
+  proc_common_gen_duty_pulse(g_pulse_active, g_pulse_period, '1', rst, clk, pulse_en, pulse);
+
+  ------------------------------------------------------------------------------
+  -- STREAM CONTROL
+  ------------------------------------------------------------------------------
+  
+  verify_snk_out.ready <= '1'                 WHEN g_flow_control=e_active  ELSE
+                          random(random'HIGH) WHEN g_flow_control=e_random  ELSE
+                          pulse               WHEN g_flow_control=e_pulse;
+  
+  
+  -- Start verify after first valid, sop or eop
+  verify_en_valid <= '1' WHEN verify_snk_in.valid='1' AND rising_edge(clk);
+  verify_en_sop   <= '1' WHEN verify_snk_in.sop='1'   AND rising_edge(clk);
+  verify_en_eop   <= '1' WHEN verify_snk_in.eop='1'   AND rising_edge(clk);
+  
+  -- Verify that the stimuli have been applied at all
+  proc_dp_verify_value("verify_snk_in.valid",            clk, verify_last, sl1, verify_en_valid);
+  proc_dp_verify_value("verify_snk_in.sop",              clk, verify_last, sl1, verify_en_sop);
+  proc_dp_verify_value("verify_snk_in.eop",              clk, verify_last, sl1, verify_en_eop);
+  proc_dp_verify_value("verify_snk_in.data",    e_equal, clk, verify_last, expected_verify_snk_in.data,    verify_snk_in_data);
+  --proc_dp_verify_value("verify_snk_in.bsn",     e_equal, clk, verify_last, expected_verify_snk_in.bsn,     verify_snk_in.bsn);
+  --proc_dp_verify_value("verify_snk_in.channel", e_equal, clk, verify_last, expected_verify_snk_in.channel, verify_snk_in.channel);
+  --proc_dp_verify_value("verify_snk_in.err",     e_equal, clk, verify_last, expected_verify_snk_in.err,     verify_snk_in.err);
+  
+  -- Verify that the output is incrementing data, like the input stimuli
+  proc_dp_verify_data("verify_snk_in.data",    c_rl, c_data_max,   c_unsigned_1, clk, verify_en_valid, verify_snk_out.ready, verify_snk_in.valid, verify_snk_in.data,    prev_verify_snk_in.data);
+  --proc_dp_verify_data("verify_snk_in.bsn",     c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop,   verify_snk_out.ready, verify_snk_in.sop,   verify_snk_in.bsn,     prev_verify_snk_in.bsn);
+  --proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop,   verify_snk_out.ready, verify_snk_in.sop,   verify_snk_in.channel, prev_verify_snk_in.channel);
+  --proc_dp_verify_data("verify_snk_in.err",     c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_eop,   verify_snk_out.ready, verify_snk_in.eop,   verify_snk_in.err,     prev_verify_snk_in.err);
+  
+  -- Verify that the output sync occurs when expected
+  --proc_dp_verify_sync(g_sync_period, g_sync_offset, clk, verify_en_sop, verify_snk_in.sync, verify_snk_in.sop, verify_snk_in.bsn);
+  
+  -- Verify output packet ctrl
+  proc_dp_verify_sop_and_eop(clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, verify_hold_sop);
+  
+  -- Verify output packet block size
+  exp_size <= g_pkt_len;
+  
+  proc_dp_verify_block_size(exp_size, clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, cnt_size);
+
+  -- Verify output ready latency
+  proc_dp_verify_valid(clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
+    
+  ------------------------------------------------------------------------------
+  -- Auxiliary
+  ------------------------------------------------------------------------------
+  
+  -- Map to slv to ease monitoring in wave window
+  verify_data  <= verify_snk_in.data(g_in_dat_w-1 DOWNTO 0);
+  
+  verify_snk_in_data <= verify_snk_in.data WHEN verify_snk_in.valid='1';
+  
+END tb;