Skip to content
Snippets Groups Projects
Commit 602d4816 authored by Pepping's avatar Pepping
Browse files

Replaced sopc by mmm

parent ab78b818
No related branches found
No related tags found
No related merge requests found
Show whitespace changes
Inline Side-by-side
applications/apertif/designs/apertif_unb1_bn_filterbank/src/vhdl/apertif_unb1_bn_filterbank.vhd
+ 137
− 483
View file @ 602d4816
......@@ -111,7 +111,7 @@ END apertif_unb1_bn_filterbank;
ARCHITECTURE str OF apertif_unb1_bn_filterbank IS
CONSTANT c_fw_version : t_unb1_board_fw_version := (3, 0); -- firmware version x.y
CONSTANT c_fw_version : t_unb1_board_fw_version := (3, 1); -- firmware version x.y
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 1, 0, 0, 1, 1);
CONSTANT c_nof_dp_phs_clk : NATURAL := 6; -- nof dp_phs_clk that can be used to detect the word phase, must be <= 6
......@@ -282,486 +282,6 @@ ARCHITECTURE str OF apertif_unb1_bn_filterbank IS
BEGIN
-----------------------------------------------------------------------------
-- SOPC system
-----------------------------------------------------------------------------
u_sopc : ENTITY work.sopc_apertif_unb1_bn_filterbank
PORT MAP (
-- 1) global signals:
clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
reset_n => xo_rst_n,
mm_clk => mm_clk, -- PLL clk[0] = 50 MHz system clock that the NIOS2 and the MM bus run on
cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
-- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
areset_to_the_altpll_0 => xo_rst,
-- the_avs_eth_0
coe_clk_export_from_the_avs_eth_0 => OPEN,
coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w-1 DOWNTO 0),
coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w-1 DOWNTO 0),
coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-- the_reg_unb_sens
coe_clk_export_from_the_reg_unb_sens => OPEN,
coe_reset_export_from_the_reg_unb_sens => OPEN,
coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_source
coe_clk_export_from_the_reg_bsn_source => OPEN,
coe_reset_export_from_the_reg_bsn_source => OPEN,
coe_address_export_from_the_reg_bsn_source => reg_bsn_source_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_source_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_bsn_source => reg_bsn_source_mosi.rd,
coe_readdata_export_to_the_reg_bsn_source => reg_bsn_source_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wr,
coe_writedata_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_scheduler_wg
coe_clk_export_from_the_reg_bsn_scheduler_wg => OPEN,
coe_reset_export_from_the_reg_bsn_scheduler_wg => OPEN,
coe_address_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.address(0), -- reg_bsn_scheduler_adr_w = 1
coe_read_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.rd,
coe_readdata_export_to_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wr,
coe_writedata_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_adc_quad
coe_clk_export_from_the_reg_adc_quad => OPEN,
coe_reset_export_from_the_reg_adc_quad => OPEN,
coe_address_export_from_the_reg_adc_quad => reg_adc_quad_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_adc_quad_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_adc_quad => reg_adc_quad_mosi.rd,
coe_readdata_export_to_the_reg_adc_quad => reg_adc_quad_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wr,
coe_writedata_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_data_buffer
coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_ram_diag_db_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_data_buffer
coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_reg_diag_db_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_wg_0
coe_clk_export_from_the_reg_diag_wg_0 => OPEN,
coe_reset_export_from_the_reg_diag_wg_0 => OPEN,
coe_address_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).rd,
coe_readdata_export_to_the_reg_diag_wg_0 => reg_wg_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wr,
coe_writedata_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_wg_1
coe_clk_export_from_the_reg_diag_wg_1 => OPEN,
coe_reset_export_from_the_reg_diag_wg_1 => OPEN,
coe_address_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).rd,
coe_readdata_export_to_the_reg_diag_wg_1 => reg_wg_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wr,
coe_writedata_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_wg_2
coe_clk_export_from_the_reg_diag_wg_2 => OPEN,
coe_reset_export_from_the_reg_diag_wg_2 => OPEN,
coe_address_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).rd,
coe_readdata_export_to_the_reg_diag_wg_2 => reg_wg_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wr,
coe_writedata_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_wg_3
coe_clk_export_from_the_reg_diag_wg_3 => OPEN,
coe_reset_export_from_the_reg_diag_wg_3 => OPEN,
coe_address_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).rd,
coe_readdata_export_to_the_reg_diag_wg_3 => reg_wg_miso_arr(3).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wr,
coe_writedata_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_wg_0
coe_clk_export_from_the_ram_diag_wg_0 => OPEN,
coe_reset_export_from_the_ram_diag_wg_0 => OPEN,
coe_address_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).rd,
coe_readdata_export_to_the_ram_diag_wg_0 => ram_wg_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wr,
coe_writedata_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_wg_1
coe_clk_export_from_the_ram_diag_wg_1 => OPEN,
coe_reset_export_from_the_ram_diag_wg_1 => OPEN,
coe_address_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).rd,
coe_readdata_export_to_the_ram_diag_wg_1 => ram_wg_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wr,
coe_writedata_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_wg_2
coe_clk_export_from_the_ram_diag_wg_2 => OPEN,
coe_reset_export_from_the_ram_diag_wg_2 => OPEN,
coe_address_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).rd,
coe_readdata_export_to_the_ram_diag_wg_2 => ram_wg_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wr,
coe_writedata_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_wg_3
coe_clk_export_from_the_ram_diag_wg_3 => OPEN,
coe_reset_export_from_the_ram_diag_wg_3 => OPEN,
coe_address_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).rd,
coe_readdata_export_to_the_ram_diag_wg_3 => ram_wg_miso_arr(3).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wr,
coe_writedata_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diagnostics_back
coe_clk_export_from_the_reg_diagnostics_back => OPEN,
coe_reset_export_from_the_reg_diagnostics_back => OPEN,
coe_address_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.rd,
coe_readdata_export_to_the_reg_diagnostics_back => reg_back_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wr,
coe_writedata_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diagnostics_mesh
coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
coe_address_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.rd,
coe_readdata_export_to_the_reg_diagnostics_mesh => reg_mesh_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wr,
coe_writedata_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_tr_nonbonded_back
coe_clk_export_from_the_reg_tr_nonbonded_back => OPEN,
coe_reset_export_from_the_reg_tr_nonbonded_back => OPEN,
coe_address_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.rd,
coe_readdata_export_to_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wr,
coe_writedata_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_tr_nonbonded_mesh
coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.rd,
coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wr,
coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_aduh_mon_0
coe_clk_export_from_the_reg_aduh_mon_0 => OPEN,
coe_reset_export_from_the_reg_aduh_mon_0 => OPEN,
coe_address_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).rd,
coe_readdata_export_to_the_reg_aduh_mon_0 => reg_mon_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wr,
coe_writedata_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_aduh_mon_1
coe_clk_export_from_the_reg_aduh_mon_1 => OPEN,
coe_reset_export_from_the_reg_aduh_mon_1 => OPEN,
coe_address_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).rd,
coe_readdata_export_to_the_reg_aduh_mon_1 => reg_mon_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wr,
coe_writedata_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_aduh_mon_2
coe_clk_export_from_the_reg_aduh_mon_2 => OPEN,
coe_reset_export_from_the_reg_aduh_mon_2 => OPEN,
coe_address_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).rd,
coe_readdata_export_to_the_reg_aduh_mon_2 => reg_mon_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wr,
coe_writedata_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_aduh_mon_3
coe_clk_export_from_the_reg_aduh_mon_3 => OPEN,
coe_reset_export_from_the_reg_aduh_mon_3 => OPEN,
coe_address_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).rd,
coe_readdata_export_to_the_reg_aduh_mon_3 => reg_mon_miso_arr(3).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wr,
coe_writedata_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_aduh_mon_0
coe_clk_export_from_the_ram_aduh_mon_0 => OPEN,
coe_reset_export_from_the_ram_aduh_mon_0 => OPEN,
coe_address_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).rd,
coe_readdata_export_to_the_ram_aduh_mon_0 => ram_mon_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wr,
coe_writedata_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_aduh_mon_1
coe_clk_export_from_the_ram_aduh_mon_1 => OPEN,
coe_reset_export_from_the_ram_aduh_mon_1 => OPEN,
coe_address_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).rd,
coe_readdata_export_to_the_ram_aduh_mon_1 => ram_mon_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wr,
coe_writedata_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_aduh_mon_2
coe_clk_export_from_the_ram_aduh_mon_2 => OPEN,
coe_reset_export_from_the_ram_aduh_mon_2 => OPEN,
coe_address_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).rd,
coe_readdata_export_to_the_ram_aduh_mon_2 => ram_mon_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wr,
coe_writedata_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_aduh_mon_3
coe_clk_export_from_the_ram_aduh_mon_3 => OPEN,
coe_reset_export_from_the_ram_aduh_mon_3 => OPEN,
coe_address_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).rd,
coe_readdata_export_to_the_ram_aduh_mon_3 => ram_mon_miso_arr(3).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wr,
coe_writedata_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_adu_i2c_commander_ab
coe_clk_export_from_the_reg_adu_i2c_commander_ab => OPEN,
coe_reset_export_from_the_reg_adu_i2c_commander_ab => OPEN,
coe_address_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).rd,
coe_readdata_export_to_the_reg_adu_i2c_commander_ab => reg_commander_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wr,
coe_writedata_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_adu_i2c_commander_cd
coe_clk_export_from_the_reg_adu_i2c_commander_cd => OPEN,
coe_reset_export_from_the_reg_adu_i2c_commander_cd => OPEN,
coe_address_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).rd,
coe_readdata_export_to_the_reg_adu_i2c_commander_cd => reg_commander_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wr,
coe_writedata_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_adu_i2c_protocol_ab
coe_clk_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
coe_reset_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
coe_address_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).rd,
coe_readdata_export_to_the_ram_adu_i2c_protocol_ab => ram_protocol_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wr,
coe_writedata_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_adu_i2c_protocol_cd
coe_clk_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
coe_reset_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
coe_address_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).rd,
coe_readdata_export_to_the_ram_adu_i2c_protocol_cd => ram_protocol_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wr,
coe_writedata_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_adu_i2c_result_ab
coe_clk_export_from_the_ram_adu_i2c_result_ab => OPEN,
coe_reset_export_from_the_ram_adu_i2c_result_ab => OPEN,
coe_address_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).rd,
coe_readdata_export_to_the_ram_adu_i2c_result_ab => ram_result_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wr,
coe_writedata_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_adu_i2c_result_cd
coe_clk_export_from_the_ram_adu_i2c_result_cd => OPEN,
coe_reset_export_from_the_ram_adu_i2c_result_cd => OPEN,
coe_address_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).rd,
coe_readdata_export_to_the_ram_adu_i2c_result_cd => ram_result_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wr,
coe_writedata_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_scheduler_sp_on
coe_clk_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
coe_reset_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
coe_address_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.address(0),
coe_read_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.rd,
coe_readdata_export_to_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wr,
coe_writedata_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_scheduler_sp_off
coe_clk_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
coe_reset_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
coe_address_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.address(0),
coe_read_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.rd,
coe_readdata_export_to_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wr,
coe_writedata_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_st_sst
coe_clk_export_from_the_ram_st_sst => OPEN,
coe_reset_export_from_the_ram_st_sst => OPEN,
coe_address_export_from_the_ram_st_sst => ram_st_sst_mosi.address(c_ram_st_sst_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_st_sst => ram_st_sst_mosi.rd,
coe_readdata_export_to_the_ram_st_sst => ram_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_st_sst => ram_st_sst_mosi.wr,
coe_writedata_export_from_the_ram_st_sst => ram_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_fil_coefs
coe_clk_export_from_the_ram_fil_coefs => OPEN,
coe_reset_export_from_the_ram_fil_coefs => OPEN,
coe_address_export_from_the_ram_fil_coefs => ram_fil_coefs_mosi.address(c_ram_fil_coefs_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_fil_coefs => ram_fil_coefs_mosi.rd,
coe_readdata_export_to_the_ram_fil_coefs => ram_fil_coefs_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_fil_coefs => ram_fil_coefs_mosi.wr,
coe_writedata_export_from_the_ram_fil_coefs => ram_fil_coefs_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_ss_ss
coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.address(c_ram_ss_ss_wide_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.rd,
coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wr,
coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_ss_reorder_in
coe_clk_export_from_the_ram_ss_reorder_in => OPEN,
coe_reset_export_from_the_ram_ss_reorder_in => OPEN,
coe_address_export_from_the_ram_ss_reorder_in => ram_ss_reorder_in_mosi.address(c_ram_ss_reorder_in_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_ss_reorder_in => ram_ss_reorder_in_mosi.rd,
coe_readdata_export_to_the_ram_ss_reorder_in => ram_ss_reorder_in_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_ss_reorder_in => ram_ss_reorder_in_mosi.wr,
coe_writedata_export_from_the_ram_ss_reorder_in => ram_ss_reorder_in_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_ss_reorder_out
coe_clk_export_from_the_ram_ss_reorder_out => OPEN,
coe_reset_export_from_the_ram_ss_reorder_out => OPEN,
coe_address_export_from_the_ram_ss_reorder_out => ram_ss_reorder_out_mosi.address(c_ram_ss_reorder_out_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_ss_reorder_out => ram_ss_reorder_out_mosi.rd,
coe_readdata_export_to_the_ram_ss_reorder_out => ram_ss_reorder_out_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_ss_reorder_out => ram_ss_reorder_out_mosi.wr,
coe_writedata_export_from_the_ram_ss_reorder_out => ram_ss_reorder_out_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_bg_ss
coe_clk_export_from_the_reg_diag_bg_ss => OPEN,
coe_reset_export_from_the_reg_diag_bg_ss => OPEN,
coe_address_export_from_the_reg_diag_bg_ss => reg_diag_bg_ss_mosi.address(c_reg_diag_bg_ss_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diag_bg_ss => reg_diag_bg_ss_mosi.rd,
coe_readdata_export_to_the_reg_diag_bg_ss => reg_diag_bg_ss_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diag_bg_ss => reg_diag_bg_ss_mosi.wr,
coe_writedata_export_from_the_reg_diag_bg_ss => reg_diag_bg_ss_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_bg_ss
coe_clk_export_from_the_ram_diag_bg_ss => OPEN,
coe_reset_export_from_the_ram_diag_bg_ss => OPEN,
coe_address_export_from_the_ram_diag_bg_ss => ram_diag_bg_ss_mosi.address(c_ram_diag_bg_ss_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_diag_bg_ss => ram_diag_bg_ss_mosi.rd,
coe_readdata_export_to_the_ram_diag_bg_ss => ram_diag_bg_ss_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_diag_bg_ss => ram_diag_bg_ss_mosi.wr,
coe_writedata_export_from_the_ram_diag_bg_ss => ram_diag_bg_ss_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_bg_pfb
coe_clk_export_from_the_reg_diag_bg_pfb => OPEN,
coe_reset_export_from_the_reg_diag_bg_pfb => OPEN,
coe_address_export_from_the_reg_diag_bg_pfb => reg_diag_bg_pfb_mosi.address(c_reg_diag_bg_pfb_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_diag_bg_pfb => reg_diag_bg_pfb_mosi.rd,
coe_readdata_export_to_the_reg_diag_bg_pfb => reg_diag_bg_pfb_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_diag_bg_pfb => reg_diag_bg_pfb_mosi.wr,
coe_writedata_export_from_the_reg_diag_bg_pfb => reg_diag_bg_pfb_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_bg_pfb
coe_clk_export_from_the_ram_diag_bg_pfb => OPEN,
coe_reset_export_from_the_ram_diag_bg_pfb => OPEN,
coe_address_export_from_the_ram_diag_bg_pfb => ram_diag_bg_pfb_mosi.address(c_ram_diag_bg_pfb_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_diag_bg_pfb => ram_diag_bg_pfb_mosi.rd,
coe_readdata_export_to_the_ram_diag_bg_pfb => ram_diag_bg_pfb_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_diag_bg_pfb => ram_diag_bg_pfb_mosi.wr,
coe_writedata_export_from_the_ram_diag_bg_pfb => ram_diag_bg_pfb_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (c_use_phy).
coe_clk_export_from_the_reg_wdi => OPEN,
coe_reset_export_from_the_reg_wdi => OPEN,
coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_debug_wave
out_port_from_the_pio_debug_wave => pout_debug_wave,
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_system_info: actually a avs_common_mm instance
coe_clk_export_from_the_pio_system_info => OPEN,
coe_reset_export_from_the_pio_system_info => OPEN,
coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_rom_system_info
coe_clk_export_from_the_rom_system_info => OPEN,
coe_reset_export_from_the_rom_system_info => OPEN,
coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_wdi
out_port_from_the_pio_wdi => pout_wdi,
-- the_reg_dp_shiftram
coe_clk_export_from_the_reg_dp_shiftram => OPEN,
coe_reset_export_from_the_reg_dp_shiftram => OPEN,
coe_address_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.address(c_reg_dp_shiftram_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.rd,
coe_readdata_export_to_the_reg_dp_shiftram => reg_dp_shiftram_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wr,
coe_writedata_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
......@@ -853,7 +373,141 @@ BEGIN
ETH_SGOUT => ETH_SGOUT
);
u_mmm : ENTITY work.mmm_apertif_unb1_bn_filterbank
GENERIC MAP(
-- General
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr
)
PORT MAP (
xo_clk => xo_clk,
xo_rst_n => xo_rst_n,
xo_rst => xo_rst,
mm_rst => mm_rst,
mm_clk => mm_clk,
mm_locked => mm_locked,
cal_clk => cal_clk,
pout_wdi => pout_wdi,
-- Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- system_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- MM bsn source
reg_bsn_source_mosi => reg_bsn_source_mosi,
reg_bsn_source_miso => reg_bsn_source_miso,
-- MM bsn scheduler for WG
reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-- MM aduh quad
reg_adc_quad_mosi => reg_adc_quad_mosi,
reg_adc_quad_miso => reg_adc_quad_miso,
-- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
reg_wg_mosi_arr => reg_wg_mosi_arr,
reg_wg_miso_arr => reg_wg_miso_arr,
ram_wg_mosi_arr => ram_wg_mosi_arr,
ram_wg_miso_arr => ram_wg_miso_arr,
-- MM signal path monitors for [A, B, C, D]
reg_mon_mosi_arr => reg_mon_mosi_arr,
reg_mon_miso_arr => reg_mon_miso_arr,
ram_mon_mosi_arr => ram_mon_mosi_arr,
ram_mon_miso_arr => ram_mon_miso_arr,
-- MM registers [0,1] for I2C access with ADUs [AB,CD]
reg_commander_mosi_arr => reg_commander_mosi_arr,
reg_commander_miso_arr => reg_commander_miso_arr,
ram_protocol_mosi_arr => ram_protocol_mosi_arr,
ram_protocol_miso_arr => ram_protocol_miso_arr,
ram_result_mosi_arr => ram_result_mosi_arr,
ram_result_miso_arr => ram_result_miso_arr,
reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
-- MM registers for fft subband statistics
ram_st_sst_mosi => ram_st_sst_mosi,
ram_st_sst_miso => ram_st_sst_miso,
-- MM registers for filter coefficients
ram_fil_coefs_mosi => ram_fil_coefs_mosi,
ram_fil_coefs_miso => ram_fil_coefs_miso,
-- MM registers for Suband Select
ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
ram_ss_reorder_in_mosi => ram_ss_reorder_in_mosi,
ram_ss_reorder_in_miso => ram_ss_reorder_in_miso,
ram_ss_reorder_out_mosi => ram_ss_reorder_out_mosi,
ram_ss_reorder_out_miso => ram_ss_reorder_out_miso,
-- MM registers for block generator
ram_diag_bg_ss_mosi => ram_diag_bg_ss_mosi,
ram_diag_bg_ss_miso => ram_diag_bg_ss_miso,
reg_diag_bg_ss_mosi => reg_diag_bg_ss_mosi,
reg_diag_bg_ss_miso => reg_diag_bg_ss_miso,
-- MM registers for pfb block generator
ram_diag_bg_pfb_mosi => ram_diag_bg_pfb_mosi,
ram_diag_bg_pfb_miso => ram_diag_bg_pfb_miso,
reg_diag_bg_pfb_mosi => reg_diag_bg_pfb_mosi,
reg_diag_bg_pfb_miso => reg_diag_bg_pfb_miso,
-- . diag_data_buffer
ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_miso,
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-- MM registers for tr_nonbonded
-- . mesh
reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
-- . back
reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
reg_back_diagnostics_miso => reg_back_diagnostics_miso,
-- MM DP shiftram
reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
reg_dp_shiftram_miso => reg_dp_shiftram_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso
);
-----------------------------------------------------------------------------
-- Specific node function
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment