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Commit 5fc5c03d authored by Pieter Donker's avatar Pieter Donker
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STAT-266: changed stamp_svn_rev to revision_id

parent 92dda5bd
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2 merge requests!28Master,!13Resolve STAT-266
...@@ -47,7 +47,7 @@ ENTITY unb2b_arp_ping IS ...@@ -47,7 +47,7 @@ ENTITY unb2b_arp_ping IS
g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model; g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF g_revision_id : STRING := ""; -- revision id -- set by QSF
g_factory_image : BOOLEAN := TRUE; g_factory_image : BOOLEAN := TRUE;
g_protect_addr_range: BOOLEAN := FALSE g_protect_addr_range: BOOLEAN := FALSE
); );
...@@ -197,7 +197,7 @@ BEGIN ...@@ -197,7 +197,7 @@ BEGIN
g_design_note => g_design_note, g_design_note => g_design_note,
g_stamp_date => g_stamp_date, g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time, g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn, g_revision_id => g_revision_id,
g_mm_clk_freq => c_mm_clk_freq, g_mm_clk_freq => c_mm_clk_freq,
g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M, g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
g_aux => c_unb2b_board_aux, g_aux => c_unb2b_board_aux,
......
...@@ -49,7 +49,7 @@ ENTITY ctrl_unb2b_board IS ...@@ -49,7 +49,7 @@ ENTITY ctrl_unb2b_board IS
g_fw_version : t_unb2b_board_fw_version := (0, 0); -- firmware version x.y g_fw_version : t_unb2b_board_fw_version := (0, 0); -- firmware version x.y
g_stamp_date : NATURAL := 0; g_stamp_date : NATURAL := 0;
g_stamp_time : NATURAL := 0; g_stamp_time : NATURAL := 0;
g_stamp_svn : NATURAL := 0; g_revision_id : STRING := "";
g_design_note : STRING := "UNUSED"; g_design_note : STRING := "UNUSED";
g_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy g_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
g_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_125M; g_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_125M;
...@@ -493,7 +493,7 @@ BEGIN ...@@ -493,7 +493,7 @@ BEGIN
g_fw_version => g_fw_version, g_fw_version => g_fw_version,
g_stamp_date => g_stamp_date, g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time, g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn, g_revision_id => g_revision_id,
g_design_note => g_design_note, g_design_note => g_design_note,
g_rom_version => c_rom_version g_rom_version => c_rom_version
) )
......
...@@ -34,7 +34,7 @@ ENTITY mms_unb2b_board_system_info IS ...@@ -34,7 +34,7 @@ ENTITY mms_unb2b_board_system_info IS
g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y
g_stamp_date : NATURAL := 0; g_stamp_date : NATURAL := 0;
g_stamp_time : NATURAL := 0; g_stamp_time : NATURAL := 0;
g_stamp_svn : NATURAL := 0; g_revision_id : STRING := "";
g_design_note : STRING := ""; g_design_note : STRING := "";
g_rom_version : NATURAL := 1; g_rom_version : NATURAL := 1;
g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux -- aux contains the hardware version g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux -- aux contains the hardware version
...@@ -109,7 +109,7 @@ BEGIN ...@@ -109,7 +109,7 @@ BEGIN
g_design_name => g_design_name, g_design_name => g_design_name,
g_stamp_date => g_stamp_date, g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time, g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn, g_revision_id => g_revision_id,
g_design_note => g_design_note g_design_note => g_design_note
) )
PORT MAP ( PORT MAP (
......
...@@ -55,7 +55,7 @@ ENTITY unb2b_board_system_info_reg IS ...@@ -55,7 +55,7 @@ ENTITY unb2b_board_system_info_reg IS
g_design_name : STRING; g_design_name : STRING;
g_stamp_date : NATURAL := 0; g_stamp_date : NATURAL := 0;
g_stamp_time : NATURAL := 0; g_stamp_time : NATURAL := 0;
g_stamp_svn : NATURAL := 0; g_revision_id : STRING := "";
g_design_note : STRING g_design_note : STRING
); );
PORT ( PORT (
...@@ -76,10 +76,19 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS ...@@ -76,10 +76,19 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
CONSTANT c_nof_fixed_regs : NATURAL := 2; -- info, use_phy CONSTANT c_nof_fixed_regs : NATURAL := 2; -- info, use_phy
CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name
CONSTANT c_nof_stamp_regs : NATURAL := 3; -- date, time, svn rev CONSTANT c_nof_stamp_regs : NATURAL := 2; -- date, time
CONSTANT c_nof_revision_id_regs : NATURAL := 3; -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note
CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs; CONSTANT c_info_reg : NATURAL := 0;
CONSTANT c_use_phy_reg : NATURAL := 1;
CONSTANT c_design_name_offset : NATURAL := c_nof_fixed_regs;
CONSTANT c_stamp_date_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs;
CONSTANT c_stamp_time_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + 1;
CONSTANT c_revision_id_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
CONSTANT c_design_note_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
CONSTANT c_mm_reg : t_c_mem := (latency => 1, CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs), adr_w => ceil_log2(c_nof_regs),
...@@ -91,6 +100,7 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS ...@@ -91,6 +100,7 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
CONSTANT c_use_phy : STD_LOGIC_VECTOR(c_use_phy_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Unused but keep for compatibillity CONSTANT c_use_phy : STD_LOGIC_VECTOR(c_use_phy_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Unused but keep for compatibillity
CONSTANT c_design_name : t_slv_32_arr(0 TO c_nof_design_name_regs-1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs); CONSTANT c_design_name : t_slv_32_arr(0 TO c_nof_design_name_regs-1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
CONSTANT c_revision_id : t_slv_32_arr(0 TO c_nof_revision_id_regs-1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
CONSTANT c_design_note : t_slv_32_arr(0 TO c_nof_design_note_regs-1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs); CONSTANT c_design_note : t_slv_32_arr(0 TO c_nof_design_note_regs-1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
BEGIN BEGIN
...@@ -111,32 +121,35 @@ BEGIN ...@@ -111,32 +121,35 @@ BEGIN
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1 sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
vA := TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0)); vA := TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0));
IF vA = 0 THEN IF vA = c_info_reg THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= info; sla_out.rddata(c_word_w-1 DOWNTO 0) <= info;
-- Use bit 11 to indicate that we're using the MM bus (not the info SLV). -- Use bit 11 to indicate that we're using the MM bus (not the info SLV).
-- Using the MM bus enables user to also read use_phy, design_name etc. -- Using the MM bus enables user to also read use_phy, design_name etc.
sla_out.rddata(11) <= '1'; sla_out.rddata(11) <= '1';
ELSIF vA = 1 THEN
ELSIF vA = c_use_phy_reg THEN
sla_out.rddata(c_use_phy_w-1 DOWNTO 0) <= c_use_phy; sla_out.rddata(c_use_phy_w-1 DOWNTO 0) <= c_use_phy;
ELSIF vA < c_nof_fixed_regs + c_nof_design_name_regs THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_name(vA-c_nof_fixed_regs);
ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs THEN ELSIF vA < c_design_name_offset + c_nof_design_name_regs THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_name(vA - c_design_name_offset);
ELSIF vA = c_stamp_date_offset THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_date, c_word_w); sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_date, c_word_w);
ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs+1 THEN ELSIF vA = c_stamp_time_offset THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_time, c_word_w); sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_time, c_word_w);
ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs+2 THEN ELSIF vA < c_revision_id_offset + c_nof_revision_id_regs THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_svn, c_word_w); sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_revision_id(vA - c_revision_id_offset);
ELSIF vA < c_nof_fixed_regs + c_nof_design_name_regs+c_nof_stamp_regs+c_nof_design_note_regs THEN ELSIF vA < c_design_note_offset + c_nof_design_note_regs THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_note(vA-c_nof_fixed_regs-c_nof_design_name_regs-c_nof_stamp_regs); sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_note(vA - c_design_note_offset);
END IF; END IF;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
......
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