Added all files in hereafterremovel of "mother" library

applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg

 hdl_lib_name = apertif_unb1_fn_beamformer_base
 hdl_library_clause_name = apertif_unb1_fn_beamformer_base_lib
-hdl_lib_uses_synth = unb1_board apertif_unb1_fn_beamformer tech_ddr_lib
+hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr
 hdl_lib_technology = ip_stratixiv
 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave
 
 synth_top_level_entity =
 
-synth_files = apertif_unb1_fn_beamformer_base.vhd
+synth_files =     
+    $HDL_BUILD_DIR/quartus/apertif_unb1_fn_beamformer_trans/sopc_apertif_unb1_fn_beamformer.vhd    
+    ../../src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
+    ../../src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd
+    ../../src/vhdl/node_apertif_unb1_fn_beamformer.vhd
+    ../../src/vhdl/apertif_unb1_fn_beamformer.vhd
+    apertif_unb1_fn_beamformer_base.vhd
     
 test_bench_files =                                                                      
+    tb_apertif_unb1_fn_beamformer_base.vhd                                       
+
+modelsim_copy_files = ../../src/hex hex                                                   
 
 quartus_copy_files = ../../quartus/sopc_apertif_unb1_fn_beamformer.sopc .
 
@@ -22,3 +31,7 @@ quartus_tcl_files =
 quartus_qip_files =
     $HDL_BUILD_DIR/quartus/apertif_unb1_fn_beamformer_base/sopc_apertif_unb1_fn_beamformer.qip
 
+modelsim_search_libraries =                                                                                            
+    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip    
+