Made a top level testbench.

applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd

@@ -285,7 +285,7 @@ BEGIN
           mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2+1,  sosi_out_not_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
         END LOOP;
       END LOOP;
-      WAIT FOR c_st_clk_period*5;
+      WAIT FOR c_st_clk_period*c_block_size;
     END LOOP;
 
 
@@ -306,7 +306,7 @@ BEGIN
           mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2+1,  sosi_out_not_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
         END LOOP;
       END LOOP;
-      WAIT FOR c_st_clk_period*2;
+      WAIT FOR c_st_clk_period*c_block_size;
     END LOOP;
 
 
@@ -314,7 +314,7 @@ BEGIN
     mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
     WAIT FOR c_mm_clk_period*300;
     mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
-    WAIT FOR c_mm_clk_period*5500;
+    WAIT FOR c_mm_clk_period*55000;
 
 
     assert false report "3. read whole memory!" severity note;
@@ -327,7 +327,7 @@ BEGIN
           mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2+1,  sosi_out_not_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
         END LOOP;
       END LOOP;
-      WAIT FOR c_st_clk_period*1;
+      WAIT FOR c_st_clk_period*c_block_size;
     END LOOP;
 
     tb_end <= '1';