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Commit 5e459fb8 authored by Eric Kooistra's avatar Eric Kooistra
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Shortened sync interval and used pps_rst to make the tb simulate faster (few... 

Shortened sync interval and used pps_rst to make the tb simulate faster (few minutes now, instead of 12 minutes).
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1 merge request!258Shortened sync interval and used pps_rst to make the tb simulate faster (few...
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applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
+ 23
− 17
View file @ 5e459fb8
......@@ -69,6 +69,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_init_bsn : NATURAL := 17; -- some recognizable value >= 0
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
......@@ -76,16 +77,16 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
CONSTANT c_nof_block_per_sync : NATURAL := 16;
CONSTANT c_nof_block_per_sync : NATURAL := 7; -- use short interval to speed up simulation
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value, due to WG rounding
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
-- WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
CONSTANT c_bsn_start_wg : NATURAL := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
CONSTANT c_ampl_sp_0 : NATURAL := c_sdp_FS_adc/2; -- = 0.5 * FS, so in number of lsb
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
......@@ -107,6 +108,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
SIGNAL tb_clk : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
SIGNAL pps_rst : STD_LOGIC := '1';
SIGNAL gen_pps : STD_LOGIC := '0';
-- WG
SIGNAL dbg_c_exp_wg_power_sp_0 : REAL := c_exp_wg_power_sp_0;
SIGNAL sp_samples : t_integer_arr(0 TO c_mon_buffer_nof_samples-1) := (OTHERS=>0);
......@@ -116,9 +120,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL ext_pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
......@@ -161,9 +163,9 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, gen_pps);
jesd204b_sysref <= gen_pps;
ext_pps <= gen_pps;
------------------------------------------------------------------------------
-- DUT
......@@ -181,7 +183,7 @@ BEGIN
PORT MAP (
-- GENERAL
CLK => ext_clk,
PPS => pps,
PPS => ext_pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
......@@ -230,15 +232,17 @@ BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
proc_common_wait_until_hi_lo(ext_clk, ext_pps);
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
-- Release PPS pulser, to get first PPS now and to start BSN source
WAIT FOR 1 us;
pps_rst <= '0';
----------------------------------------------------------------------------
-- Enable WG
......@@ -265,9 +269,11 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
"UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3, -- this is the wait until condition
----------------------------------------------------------------------------
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
"UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync*2, -- this is the wait until condition
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
......
applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
+ 24
− 18
View file @ 5e459fb8
......@@ -69,6 +69,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc IS
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0);
CONSTANT c_init_bsn : NATURAL := 17; -- some recognizable value >= 0
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
......@@ -76,16 +77,16 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc IS
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
CONSTANT c_nof_block_per_sync : NATURAL := 16;
CONSTANT c_nof_block_per_sync : NATURAL := 7; -- use short interval to speed up simulation
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value, due to WG rounding
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
-- WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
CONSTANT c_bsn_start_wg : NATURAL := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
CONSTANT c_ampl_sp_0 : NATURAL := c_sdp_FS_adc/2; -- = 0.5 * FS, so in number of lsb
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
......@@ -107,6 +108,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc IS
SIGNAL tb_clk : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
SIGNAL pps_rst : STD_LOGIC := '1';
SIGNAL gen_pps : STD_LOGIC := '0';
-- WG
SIGNAL dbg_c_exp_wg_power_sp_0 : REAL := c_exp_wg_power_sp_0;
SIGNAL sp_samples : t_integer_arr(0 TO c_mon_buffer_nof_samples-1) := (OTHERS=>0);
......@@ -116,9 +120,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc IS
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL ext_pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL ext_pps : STD_LOGIC := '0';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
......@@ -151,9 +153,9 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, gen_pps);
jesd204b_sysref <= gen_pps;
ext_pps <= gen_pps;
------------------------------------------------------------------------------
-- DUT
......@@ -171,7 +173,7 @@ BEGIN
PORT MAP (
-- GENERAL
CLK => ext_clk,
PPS => pps,
PPS => ext_pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
......@@ -212,16 +214,18 @@ BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
proc_common_wait_until_hi_lo(ext_clk, ext_pps);
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
-- Release PPS pulser, to get first PPS now and to start BSN source
WAIT FOR 1 us;
pps_rst <= '0';
----------------------------------------------------------------------------
-- Enable WG
----------------------------------------------------------------------------
......@@ -247,9 +251,11 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
"UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3, -- this is the wait until condition
----------------------------------------------------------------------------
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
"UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync*2, -- this is the wait until condition
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
......
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