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Commit 5ddf6ee6 authored by Eric Kooistra's avatar Eric Kooistra
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Improve debugging common_reg_r_w.vhd.

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1 merge request!279Improve debugging common_reg_r_w.vhd.
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...@@ -86,6 +86,11 @@ ARCHITECTURE rtl OF common_reg_r_w IS ...@@ -86,6 +86,11 @@ ARCHITECTURE rtl OF common_reg_r_w IS
CONSTANT c_pipeline : NATURAL := g_reg.latency - c_rd_latency; CONSTANT c_pipeline : NATURAL := g_reg.latency - c_rd_latency;
CONSTANT c_pipe_dat_w : NATURAL := 1 + g_reg.dat_w; -- pipeline rd_val & rd_dat together CONSTANT c_pipe_dat_w : NATURAL := 1 + g_reg.dat_w; -- pipeline rd_val & rd_dat together
TYPE t_reg_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_reg.dat_w-1 DOWNTO 0);
SIGNAL in_reg_arr : t_reg_arr(g_reg.nof_dat-1 DOWNTO 0);
SIGNAL out_reg_arr : t_reg_arr(g_reg.nof_dat-1 DOWNTO 0);
SIGNAL pipe_dat_in : STD_LOGIC_VECTOR(c_pipe_dat_w-1 DOWNTO 0); SIGNAL pipe_dat_in : STD_LOGIC_VECTOR(c_pipe_dat_w-1 DOWNTO 0);
SIGNAL pipe_dat_out : STD_LOGIC_VECTOR(c_pipe_dat_w-1 DOWNTO 0); SIGNAL pipe_dat_out : STD_LOGIC_VECTOR(c_pipe_dat_w-1 DOWNTO 0);
...@@ -104,6 +109,12 @@ BEGIN ...@@ -104,6 +109,12 @@ BEGIN
out_reg <= i_out_reg; out_reg <= i_out_reg;
-- View as reg_arr
gen_reg_arr : FOR I IN 0 TO g_reg.nof_dat-1 GENERATE
in_reg_arr(I) <= in_reg((i+1)*g_reg.dat_w-1 DOWNTO i*g_reg.dat_w);
out_reg_arr(I) <= i_out_reg((i+1)*g_reg.dat_w-1 DOWNTO i*g_reg.dat_w);
END GENERATE;
-- Pipeline to support read data latency > 1 -- Pipeline to support read data latency > 1
u_pipe_rd : ENTITY work.common_pipeline u_pipe_rd : ENTITY work.common_pipeline
GENERIC MAP ( GENERIC MAP (
...@@ -153,10 +164,10 @@ BEGIN ...@@ -153,10 +164,10 @@ BEGIN
nxt_reg_rd_arr <= (OTHERS=>'0'); nxt_reg_rd_arr <= (OTHERS=>'0');
nxt_rd_dat <= int_rd_dat; nxt_rd_dat <= int_rd_dat;
IF rd_en = '1' THEN IF rd_en = '1' THEN
FOR i IN 0 TO g_reg.nof_dat-1 LOOP FOR I IN 0 TO g_reg.nof_dat-1 LOOP
IF UNSIGNED(rd_adr) = i THEN IF UNSIGNED(rd_adr) = I THEN
nxt_reg_rd_arr(I) <= '1'; nxt_reg_rd_arr(I) <= '1';
nxt_rd_dat <= in_reg((i+1)*g_reg.dat_w-1 DOWNTO i*g_reg.dat_w); nxt_rd_dat <= in_reg((I+1)*g_reg.dat_w-1 DOWNTO I*g_reg.dat_w);
END IF; END IF;
END LOOP; END LOOP;
END IF; END IF;
...@@ -165,9 +176,9 @@ BEGIN ...@@ -165,9 +176,9 @@ BEGIN
nxt_out_reg <= i_out_reg; nxt_out_reg <= i_out_reg;
IF wr_en = '1' THEN IF wr_en = '1' THEN
FOR i IN 0 TO g_reg.nof_dat-1 LOOP FOR i IN 0 TO g_reg.nof_dat-1 LOOP
IF UNSIGNED(wr_adr) = i THEN IF UNSIGNED(wr_adr) = I THEN
nxt_reg_wr_arr(I) <= '1'; nxt_reg_wr_arr(I) <= '1';
nxt_out_reg((i+1)*g_reg.dat_w-1 DOWNTO i*g_reg.dat_w) <= wr_dat; nxt_out_reg((I+1)*g_reg.dat_w-1 DOWNTO I*g_reg.dat_w) <= wr_dat;
END IF; END IF;
END LOOP; END LOOP;
END IF; END IF;
......
...@@ -40,6 +40,12 @@ USE work.common_pkg.ALL; ...@@ -40,6 +40,12 @@ USE work.common_pkg.ALL;
PACKAGE tb_common_pkg IS PACKAGE tb_common_pkg IS
-- Constants -- Constants
-- For common_reg_r_w_dc.vhd with c_meta_delay_len = 3 and internal g_readback = TRUE a
-- c_common_cross_clock_domain_latency = 20 is enough. With g_readback = FALSE somewhat
-- more is needed, because the read register value has to cross the clock domain back
-- again, so then use proc_common_wait_cross_clock_domain_latency() with c_nof_cycles
-- = c_common_cross_clock_domain_latency * 2.
CONSTANT c_common_cross_clock_domain_latency : NATURAL := 20; CONSTANT c_common_cross_clock_domain_latency : NATURAL := 20;
......
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