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RTSD
HDL
Commits
5dd6b21f
Commit
5dd6b21f
authored
7 years ago
by
Eric Kooistra
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Added multi tb.
parent
66ae8717
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applications/apertif/designs/apertif_unb1_correlator/tb/vhdl/tb_tb_node_apertif_unb1_correlator_processing_output.vhd
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.../tb_tb_node_apertif_unb1_correlator_processing_output.vhd
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applications/apertif/designs/apertif_unb1_correlator/tb/vhdl/tb_tb_node_apertif_unb1_correlator_processing_output.vhd
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5dd6b21f
-------------------------------------------------------------------------------
--
-- Copyright (C) 2017
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Author: E. Kooistra, 6 Jun 2018
-- Purpose: Multi test bench for tb_node_apertif_unb1_correlator_processing_output
-- Desription:
-- Usage:
-- > as 4
-- > run -a
LIBRARY
IEEE
,
common_lib
;
USE
IEEE
.
std_logic_1164
.
ALL
;
USE
common_lib
.
tb_common_pkg
.
ALL
;
ENTITY
tb_tb_node_apertif_unb1_correlator_processing_output
IS
END
tb_tb_node_apertif_unb1_correlator_processing_output
;
ARCHITECTURE
tb
OF
tb_tb_node_apertif_unb1_correlator_processing_output
IS
CONSTANT
c_tb_end_vec
:
STD_LOGIC_VECTOR
(
15
DOWNTO
0
)
:
=
(
OTHERS
=>
'1'
);
SIGNAL
tb_end_vec
:
STD_LOGIC_VECTOR
(
15
DOWNTO
0
)
:
=
c_tb_end_vec
;
-- sufficiently long to fit all tb instances
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
-- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
BEGIN
-- DUT settings
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_nof_bg_sync : NATURAL := 2; -- [t] number of BG sync intervals, is number ofintegration intervals
-- -- DUT settings
-- g_nof_pn : NATURAL := 2; -- number of PN, choose >= 1
-- g_nof_10G : NATURAL := 2; -- number of 10G input per PN, choose >= 2 and even (to fit Q_interleave=2)
-- g_nof_beamlets : NATURAL := 2; -- [bu_i], is 88 in 8bit, 120 in 6bit beamlet mode
-- g_nof_tchan_per_sync : NATURAL := 10; -- [t_c], is 12500, choose > number of taps of WPFB to simulate longer than the FIR impulse response
-- g_inter_channel_delay : NATURAL := 279; -- throttle correlator output
-- g_use_wpfb : BOOLEAN := TRUE;
-- g_use_prefilter : BOOLEAN := TRUE;
-- g_use_prefilter_ones : BOOLEAN := FALSE;
-- -- BG settings
-- g_bg_duty_cycle_gap : NATURAL := 54; -- small for faster simulation, use N_clk - Q_interleave*g_nof_beamlets for HW
-- --g_bg_duty_cycle_gap : NATURAL := 256; -- use 256 to default to N_clk - Q_interleave*g_nof_beamlets for HW
-- g_phasor_ampl : REAL := 0.25; -- range 0:1 where by 1.0 corresponds to maximum +amplitude, use <= 1.0 / 2**c_wpfb_fil_in_backoff_w
-- g_phasor_freq : REAL := 1.0; -- for N=64 point FFT choose channel in range -32.0 : 0.0 : 31.0
-- g_phasor_phase : REAL := 0.0 -- [0:2pi>, has nearly no effect on correlator output, because all inputs use the same phasor
u_tp_4_gap_54
:
ENTITY
work
.
tb_node_apertif_unb1_correlator_processing_output
GENERIC
MAP
(
FALSE
,
2
,
2
,
2
,
2
,
10
,
279
,
TRUE
,
TRUE
,
FALSE
,
54
,
0
.
25
,
1
.
0
,
0
.
0
)
PORT
MAP
(
tb_end_vec
(
0
));
u_tp_4_gap_256
:
ENTITY
work
.
tb_node_apertif_unb1_correlator_processing_output
GENERIC
MAP
(
FALSE
,
2
,
2
,
2
,
2
,
10
,
279
,
TRUE
,
TRUE
,
FALSE
,
256
,
0
.
25
,
1
.
0
,
0
.
0
)
PORT
MAP
(
tb_end_vec
(
1
));
tb_end
<=
'1'
WHEN
tb_end_vec
=
c_tb_end_vec
ELSE
'0'
;
p_tb_end
:
PROCESS
BEGIN
WAIT
UNTIL
tb_end
=
'1'
;
WAIT
FOR
1
ns
;
REPORT
"Multi tb simulation finished."
SEVERITY
FAILURE
;
WAIT
;
END
PROCESS
;
END
tb
;
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