Save

applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg

 hdl_lib_name = lofar2_unb2c_ddrctrl
 hdl_library_clause_name = lofar2_unb2c_ddrctrl_lib
-hdl_lib_uses_synth = common technology mm unb2c_board lofar2_ddrctrl diag dp
+hdl_lib_uses_synth = lofar2_ddrctrl common technology mm unb2c_board lofar2_ddrctrl diag dp tech_ddr lofar2_sdp mm
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e2sg
 
@@ -17,12 +17,14 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files = 
+    src/data data
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files =
     quartus .
+    src/data data
 
 quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf

applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd

@@ -20,7 +20,7 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, ddrctrl_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, lofar2_ddrctrl_lib, tech_ddr_lib, lofar2_sdp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -28,6 +28,11 @@ USE common_lib.common_mem_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE unb2c_board_lib.unb2c_board_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+
+
 
 ENTITY lofar2_unb2c_ddrctrl IS
   GENERIC (
@@ -84,7 +89,7 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
   CONSTANT c_bsn_nof_clk_per_sync   : NATURAL := sel_a_b(g_sim, 16*c_bs_block_size, c_sdp_N_clk_per_sync);
 
   -- ddrctrl
-  CONSTANT c_tech_ddr               : t_c_tech_ddr          :=c_tech_ddr4_8g_1600m;
+  CONSTANT c_tech_ddr               : t_c_tech_ddr          := func_tech_sel_ddr(g_sim, c_tech_ddr4_sim_16k, c_tech_ddr4_8g_1600m);
   CONSTANT c_stop_percentage        : NATURAL               := 80;
 
   -- diag_data_buffer
@@ -102,10 +107,10 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
   SIGNAL xo_rst                     : STD_LOGIC;
   SIGNAL xo_rst_n                   : STD_LOGIC;
   SIGNAL mm_clk                     : STD_LOGIC;
-  SIGNAL mm_rst                     : STD_LOGIC;
+  SIGNAL mm_rst                     : STD_LOGIC := '0';
   SIGNAL st_pps                     : STD_LOGIC;
   
-  SIGNAL st_rst                     : STD_LOGIC;
+  SIGNAL st_rst                     : STD_LOGIC := '0';
   SIGNAL st_clk                     : STD_LOGIC;
 
   -- PIOs
@@ -172,12 +177,20 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
   -- bsn_source_v2
   SIGNAL  reg_bsn_source_v2_mosi    : t_mem_mosi;
   SIGNAL  reg_bsn_source_v2_miso    : t_mem_miso;
+  SIGNAL  bs_sosi                   : t_dp_sosi;
 
   -- bsn_scheduler
   SIGNAL  reg_bsn_scheduler_wg_mosi : t_mem_mosi;
   SIGNAL  reg_bsn_scheduler_wg_miso : t_mem_miso;
   SIGNAL  trigger_wg                : STD_LOGIC;
 
+  -- diag_wg_wideband_arr
+  SIGNAL  reg_wg_mosi               : t_mem_mosi;
+  SIGNAL  reg_wg_miso               : t_mem_miso;
+  SIGNAL  ram_wg_mosi               : t_mem_mosi;
+  SIGNAL  ram_wg_miso               : t_mem_miso;
+  SIGNAL  wg_sosi_arr               : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+
   -- stop_in
   SIGNAL  reg_stop_in_mosi          : t_mem_mosi;
   SIGNAL  reg_stop_in_miso          : t_mem_miso;
@@ -199,7 +212,7 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
   SIGNAL  ram_data_buf_miso         : t_mem_miso;
   SIGNAL  reg_rx_seq_data_mosi      : t_mem_mosi;
   SIGNAL  reg_rx_seq_data_miso      : t_mem_miso;
-  SIGNAL  out_wr_data_ready_arr     : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
+  SIGNAL  out_wr_data_done_arr      : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
 
   -- bsn_buffer
   SIGNAL  reg_bsn_buf_mosi          : t_mem_mosi;
@@ -208,7 +221,7 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
   SIGNAL  ram_bsn_buf_miso          : t_mem_miso;
   SIGNAL  reg_rx_seq_bsn_mosi       : t_mem_mosi;
   SIGNAL  reg_rx_seq_bsn_miso       : t_mem_miso;
-  SIGNAL  out_wr_bsn_ready_arr      : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
+  SIGNAL  out_wr_bsn_done_arr       : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
 
 
 
@@ -216,11 +229,12 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
 BEGIN
 
 
-  out_siso.ready        <= vector_or(out_wr_ready_arr) OR vector_or(out_wr_bsn_ready_arr);
+  out_siso.ready        <= vector_or(NOT out_wr_data_done_arr) OR vector_or(NOT out_wr_bsn_done_arr);
+
 
-  FOR I IN 0 TO g_nof_streams-1 LOOP
+  store_bsn_in_re : FOR I IN 0 TO c_nof_streams-1 GENERATE
     out_sosi_arr(I).re  <= out_sosi_arr(I).bsn;
-  END LOOP;
+  END GENERATE;
 
   u_bsn_source_v2 : ENTITY dp_lib.mms_dp_bsn_source_v2
   GENERIC MAP (
@@ -281,7 +295,7 @@ BEGIN
     -- Basic WG parameters, see diag_wg.vhd for their meaning
     g_buf_dat_w          => c_wg_buf_dat_w,
     g_buf_addr_w         => c_wg_buf_addr_w,
-    g_calc_support       => TRUE,
+    g_calc_support       => FALSE,
     g_calc_gain_w        => 1,
     g_calc_dat_w         => c_sdp_W_adc
   )
@@ -330,10 +344,9 @@ BEGIN
     in_reg              => stop_in_arr,
     out_reg             => stop_in_arr
   );
-END mms_common_reg;
 
 
-  u_ddrctrl : ENTITY ddrctrl_lib.ddrctrl
+  u_ddrctrl : ENTITY lofar2_ddrctrl_lib.ddrctrl
   GENERIC MAP (
     g_tech_ddr        => c_tech_ddr,
     g_sim_model       => g_sim,
@@ -360,7 +373,7 @@ END mms_common_reg;
     phy4_ou           => phy4_ou
   );
 
-  u_diag_data_buffer ENTITY diag.mms_diag_data_buffer_dev
+  u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer_dev
   GENERIC MAP (    
     g_technology      => g_technology,
 
@@ -375,17 +388,17 @@ END mms_common_reg;
     g_use_steps       => FALSE,
     g_nof_steps       => c_diag_seq_rx_reg_nof_steps,
     g_seq_dat_w       => c_data_w
-  );
-  PORT (
+  )
+  PORT MAP (
     -- Memory-mapped clock domain
     mm_rst            => mm_rst,
     mm_clk            => mm_clk,
 
     reg_data_buf_mosi => reg_data_buf_mosi,
-    reg_data_buf_miso => reg_data_buf_mosi,
+    reg_data_buf_miso => reg_data_buf_miso,
 
     ram_data_buf_mosi => ram_data_buf_mosi,
-    ram_data_buf_miso => ram_data_buf_mosi,
+    ram_data_buf_miso => ram_data_buf_miso,
 
     reg_rx_seq_mosi   => reg_rx_seq_data_mosi,
     reg_rx_seq_miso   => reg_rx_seq_data_miso,
@@ -394,13 +407,13 @@ END mms_common_reg;
     dp_rst            => st_rst,
     dp_clk            => st_clk,
     
-    in_sync           => sync,
-    in_sosi_arr       => out_sosi_arr
+    in_sync           => PPS,
+    in_sosi_arr       => out_sosi_arr,
     out_wr_done_arr   => out_wr_data_done_arr
   );
 
 
-  u_diag_bsn_buffer ENTITY diag.mms_diag_data_buffer_dev
+  u_diag_bsn_buffer : ENTITY diag_lib.mms_diag_data_buffer_dev
   GENERIC MAP (    
     g_technology      => g_technology,
 
@@ -415,17 +428,17 @@ END mms_common_reg;
     g_use_steps       => FALSE,
     g_nof_steps       => c_diag_seq_rx_reg_nof_steps,
     g_seq_dat_w       => c_data_w
-  );
-  PORT (
+  )
+  PORT MAP (
     -- Memory-mapped clock domain
     mm_rst            => mm_rst,
     mm_clk            => mm_clk,
 
     reg_data_buf_mosi => reg_bsn_buf_mosi,
-    reg_data_buf_miso => reg_bsn_buf_mosi,
+    reg_data_buf_miso => reg_bsn_buf_miso,
 
     ram_data_buf_mosi => ram_bsn_buf_mosi,
-    ram_data_buf_miso => ram_bsn_buf_mosi,
+    ram_data_buf_miso => ram_bsn_buf_miso,
 
     reg_rx_seq_mosi   => reg_rx_seq_bsn_mosi,
     reg_rx_seq_miso   => reg_rx_seq_bsn_miso,
@@ -434,8 +447,8 @@ END mms_common_reg;
     dp_rst            => st_rst,
     dp_clk            => st_clk,
     
-    in_sync           => sync,
-    in_sosi_arr       => out_sosi_arr
+    in_sync           => PPS,
+    in_sosi_arr       => out_sosi_arr,
     out_wr_done_arr   => out_wr_bsn_done_arr
   );
 

applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd

@@ -130,7 +130,7 @@ ENTITY mmm_lofar2_unb2c_ddrctrl IS
     ram_bsn_buf_mosi          : OUT t_mem_mosi;
     ram_bsn_buf_miso          : IN  t_mem_miso;
     reg_rx_seq_bsn_mosi       : OUT t_mem_mosi;
-    reg_rx_seq_bsn_miso       : IN  t_mem_miso;
+    reg_rx_seq_bsn_miso       : IN  t_mem_miso
 
 
 

applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd

@@ -41,7 +41,7 @@
 --     > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
-LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, technology_lib, mm_lib, dp_lib, tech_ddr_lib, lofar2_sdp_lib, diag_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
@@ -49,6 +49,14 @@ USE unb2c_board_lib.unb2c_board_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
 USE i2c_lib.i2c_dev_unb2_pkg.ALL;
 USE i2c_lib.i2c_commander_unb2_pmbus_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+
 
 ENTITY tb_lofar2_unb2c_ddrctrl IS
     GENERIC (
@@ -70,14 +78,53 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
   CONSTANT c_fw_version      : t_unb2c_board_fw_version := (1, 0);
 
   CONSTANT c_cable_delay     : TIME := 12 ns;
-  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoard
-  CONSTANT c_clk_period      : TIME := 5 ns; 
+  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoardi
+  CONSTANT c_st_clk_period   : TIME := 5 ns;  -- 200 MHz st clk
+  CONSTANT c_tb_clk_period   : TIME := 1 ns;  -- 1000 MHz mm clk
   CONSTANT c_pps_period      : NATURAL := 1000; 
 
+  CONSTANT c_mm_file_reg_bsn_source_v2        : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+  CONSTANT c_mm_file_reg_bsn_scheduler_wg     : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+  CONSTANT c_mm_file_reg_diag_wg_wideband_arr : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG_WIDEBAND_ARR";
+  CONSTANT c_mm_file_reg_stop_in              : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STOP_IN";
+  CONSTANT c_mm_file_reg_data_buf             : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DATA_BUF";
+  CONSTANT c_mm_file_ram_data_buf             : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_DATA_BUF";
+  CONSTANT c_mm_file_reg_rx_seq_data          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_RX_SEQ_DATA";
+  CONSTANT c_mm_file_reg_bsn_buf              : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_BUF";
+  CONSTANT c_mm_file_ram_bsn_buf              : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_BSN_BUF";
+  CONSTANT c_mm_file_reg_rx_seq_bsn           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_RX_SEQ_BSN";
+
+  -- c_check_vector
+  CONSTANT  c_tech_ddr       : t_c_tech_ddr            := c_tech_ddr4_sim_16k;
+  CONSTANT  c_ctrl_data_w    : NATURAL                 := func_tech_ddr_ctlr_data_w(c_tech_ddr);                             -- 576
+  CONSTANT  c_adr_w          : NATURAL                 := func_tech_ddr_ctlr_address_w(c_tech_ddr);                          -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+  CONSTANT  c_max_adr        : NATURAL                 := 2**(c_adr_w)-1;                                                    -- the maximal address that is possible within the address vector length
+  CONSTANT  c_block_size     : NATURAL                 := 1024;
+  CONSTANT  c_nof_streams    : NATURAL                 := 12;
+  CONSTANT  c_data_w         : NATURAL                 := 14;
+  CONSTANT  c_bim            : NATURAL                 := (c_max_adr*c_ctrl_data_w)/(c_block_size*c_nof_streams*c_data_w);   -- the amount of whole blocks that fit in memory.
+
+
+  CONSTANT c_check_vector    : STD_LOGIC_VECTOR(c_ctrl_data_w*c_bim*c_block_size-1 DOWNTO 0) := (OTHERS => '0'); -- the sinewave of one stream for c_bim length
+
+  -- BSN
+  CONSTANT c_init_bsn             : NATURAL := 17;  -- some recognizable value >= 0
+  CONSTANT c_nof_block_per_sync   : NATURAL := 16;
+  CONSTANT c_nof_clk_per_sync     : NATURAL := c_nof_block_per_sync * c_sdp_N_fft;
+
+  -- WG
+  CONSTANT c_wg_phase         : REAL      := 0.0;   -- WG phase in degrees
+  CONSTANT c_wg_freq          : REAL      := 160.0; -- WG freq
+  CONSTANT c_wg_ampl          : REAL      := 20.0;  -- WG amplitude
+  CONSTANT c_bsn_start_wg     : NATURAL   := c_init_bsn + 2;  -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+
   -- DUT
-  SIGNAL clk                 : STD_LOGIC := '0';
+  SIGNAL st_clk              : STD_LOGIC := '0';
+  SIGNAL tb_clk              : STD_LOGIC := '0';
+  SIGNAL tb_end              : STD_LOGIC := '0';
   SIGNAL pps                 : STD_LOGIC := '0';
   SIGNAL pps_rst             : STD_LOGIC := '0';
+  SIGNAL rd_data             : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '0');
 
   SIGNAL WDI                 : STD_LOGIC;
   SIGNAL INTA                : STD_LOGIC;
@@ -93,13 +140,16 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
 
   SIGNAL qsfp_led            : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
 
+  SIGNAL current_bsn_wg      : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+
 BEGIN
 
   ----------------------------------------------------------------------------
   -- System setup
   ----------------------------------------------------------------------------
-  clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
-  eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
+  st_clk     <= NOT st_clk OR tb_end AFTER c_st_clk_period/2;        -- External clock (200 MHz)
+  eth_clk(0) <= NOT eth_clk(0) OR tb_end AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
   
   INTA <= 'H';  -- pull up
   INTB <= 'H';  -- pull up
@@ -107,7 +157,7 @@ BEGIN
   ------------------------------------------------------------------------------
   -- External PPS
   ------------------------------------------------------------------------------  
-  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, st_clk, pps);
 
   ------------------------------------------------------------------------------
   -- 1GbE Loopback model
@@ -129,7 +179,7 @@ BEGIN
     )
     PORT MAP (
       -- GENERAL
-      CLK         => clk,
+      CLK         => st_clk,
       PPS         => pps,
       WDI         => WDI,
       INTA        => INTA,
@@ -148,4 +198,66 @@ BEGIN
       QSFP_LED    => qsfp_led
     );
 
+
+  ------------------------------------------------------------------------------
+  -- MM slave accesses via file IO
+  ------------------------------------------------------------------------------
+  tb_clk <= NOT tb_clk OR tb_end AFTER c_tb_clk_period/2;    -- Testbench MM clock
+
+
+
+  p_mm_stimuli : PROCESS
+
+  VARIABLE v_bsn    : NATURAL  := 0;
+
+  BEGIN
+
+    ----------------------------------------------------------------------------
+    -- Enable BSN
+    ----------------------------------------------------------------------------
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2,         c_init_bsn, tb_clk);  -- Init BSN
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3,                  0, tb_clk);  -- Write high part activates the init BSN
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk);  -- nof_block_per_sync
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0,       16#00000003#, tb_clk);  -- Enable BSN at PPS
+
+
+
+    --mmf_mm_bus_rd(c_mm_file_reg_dp_selector, 0, rd_data, tb_clk);
+
+    ----------------------------------------------------------------------------
+    -- Enable and start WG
+    ----------------------------------------------------------------------------
+    --   0 : mode[7:0]           --> off=0, calc=1, repeat=2, single=3)
+    --       nof_samples[31:16]  --> <= c_ram_wg_size=1024
+    --   1 : phase[15:0]
+    --   2 : freq[30:0]
+    --   3 : ampl[16:0]
+
+    FOR I IN 0 TO c_nof_streams-1 LOOP
+      mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+0, 1024*2**16 + 1, tb_clk);      -- nof_samples, mode calc
+      mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+1, INTEGER(c_wg_phase), tb_clk); -- phase offset in degrees
+      mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+2, INTEGER(c_wg_freq), tb_clk);  -- freq
+      mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+3, INTEGER(c_wg_ampl), tb_clk);  -- ampl
+    END LOOP;
+
+    -- Read current BSN
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO  0), tb_clk);
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+    proc_common_wait_some_cycles(tb_clk, 1);
+
+    -- Write scheduler BSN to trigger start of WG at next block
+    v_bsn := TO_UINT(current_bsn_wg) + 2;
+    ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & NATURAL'image(v_bsn) & " > " & NATURAL'image(c_bsn_start_wg) SEVERITY ERROR;
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk);  -- first write low then high part
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1,              0, tb_clk);  -- assume v_bsn < 2**31-1
+
+
+    WAIT FOR c_st_clk_period*100000;
+    tb_end <= '1';
+    ASSERT FALSE  REPORT "Test: OK" SEVERITY FAILURE;
+    WAIT;
+  END PROCESS;
+
+
+
 END tb;

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd

@@ -128,7 +128,8 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
   wr_sosi                     : t_dp_sosi;
   END RECORD;
 
-  CONSTANT c_t_reg_init       : t_reg         := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
+
+  CONSTANT c_t_reg_init       : t_reg         := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '0', '1', '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
 
 
   -- signals for readability
@@ -159,6 +160,11 @@ BEGIN
       v.dvr_mosi.wr                                               := '1';
       v.wr_sosi.valid                                             := '1';
 
+      IF rst = '0' THEN
+        v.state := WAIT_FOR_SOP;
+      END IF;
+
+
 
     WHEN WAIT_FOR_SOP =>
     v.dvr_mosi.burstbegin := '0';
@@ -425,14 +431,6 @@ BEGIN
       END IF;
       -- the statemachine goes to Idle when its finished or when its waiting on other components.
 
-    WHEN OTHERS =>
-      v := c_t_reg_init;
-
-
-    END CASE;
-
-
-    IF q_reg.state = RESET OR q_reg.state = IDLE THEN
       IF stop_in = '1' THEN
         v.ready_for_set_stop := '1';
       ELSIF q_reg.ready_for_set_stop = '1' AND inp_sosi.eop = '1' THEN
@@ -446,7 +444,15 @@ BEGIN
       ELSE
         v.state := IDLE;
       END IF;
-    END IF;
+
+
+
+    WHEN OTHERS =>
+      v := c_t_reg_init;
+
+
+    END CASE;
+
 
 
     IF rst = '1' THEN

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd

@@ -129,10 +129,11 @@ BEGIN
 
 
     WHEN IDLE =>
-    -- after a reset skip the first data block so the ddr memory can initialize.
+    -- after a reset wait for a sop so the memory will be filled with whole blocks.
     IF in_sosi.sop = '1' THEN
       v.bsn_passed := '1';
     END IF;
+    v.out_sosi.valid := '0';
 
 
     END CASE;