SVN copied serializer.vhd, deserializer.vhd and sim_gx.vhd to...

SVN copied serializer.vhd, deserializer.vhd and sim_gx.vhd to technology/transceiver/ in RadioHDL/ and renamed them with prefix 'sim_transceiver_'.

libraries/io/tr_nonbonded/hdllib.cfg

@@ -7,9 +7,6 @@ build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
-    $UNB/Firmware/modules/tr_nonbonded/tb/vhdl/serializer.vhd
-    $UNB/Firmware/modules/tr_nonbonded/tb/vhdl/deserializer.vhd
-    $UNB/Firmware/modules/tr_nonbonded/tb/vhdl/sim_gx.vhd
     src/vhdl/tr_nonbonded.vhd
     $UNB/Firmware/modules/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
     $UNB/Firmware/modules/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd

libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd

@@ -165,7 +165,7 @@ BEGIN
 
   gen_sim: IF g_sim = TRUE AND g_sim_level = 1 GENERATE
     -- Behavioural serdes model (fast)
-    u_sim_gx: ENTITY WORK.sim_gx 
+    u_sim_gx: ENTITY tech_transceiver_lib.sim_transceiver_gx 
     GENERIC MAP (
       g_data_w        => g_data_w,
       g_nof_gx        => g_nof_gx,

libraries/technology/transceiver/hdllib.cfg

@@ -7,6 +7,10 @@ build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
+    sim_transceiver_serializer.vhd
+    sim_transceiver_deserializer.vhd
+    sim_transceiver_gx.vhd
+    
     tech_transceiver_component_pkg.vhd
     tech_transceiver_rx_order.vhd
     tech_transceiver_rx_align.vhd

libraries/technology/transceiver/sim_transceiver_deserializer.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose:
+--   Basic deserializer model for fast transceiver simulation
+-- Description:
+--   See sim_transceiver_serializer.vhd 
+-- Remarks:
+
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY sim_transceiver_deserializer IS 
+  GENERIC(
+    g_data_w     : NATURAL := 32;
+    g_line_rate  : NATURAL := 6250 -- In Mbps. This yields rx_clk = ((8/10)*line_rate)/g_data_w
+  );      
+  PORT(
+    tb_end       : IN  STD_LOGIC := '0';  -- in simulation stop internal clocks when tb_end='1' to support 'run -all'
+    
+    tr_clk       : IN  STD_LOGIC;
+    tr_rst       : IN  STD_LOGIC;
+
+    rx_clk       : OUT STD_LOGIC;
+    rx_rst       : OUT STD_LOGIC;
+
+    rx_out_data  : OUT STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+    rx_out_ctrl  : OUT STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+
+    rx_in        : IN  STD_LOGIC
+  );
+
+END sim_transceiver_deserializer;
+
+
+ARCHITECTURE beh OF sim_transceiver_deserializer IS
+
+  CONSTANT c_line_clk_per     : TIME := 1000000 ps /g_line_rate; --e.g. 160 ps line clk period for 6250 Mbps
+  CONSTANT c_usr_nof_bytes    : NATURAL := g_data_w / c_byte_w;
+
+  CONSTANT c_rx_clk_per       : TIME := c_line_clk_per * ( (g_data_w*10)/8 );
+
+  SIGNAL i_rx_clk             : STD_LOGIC := '1';
+  SIGNAL i_rx_rst             : STD_LOGIC := '1';
+
+BEGIN
+
+  rx_clk   <= i_rx_clk;
+  rx_rst   <= i_rx_rst;
+  i_rx_clk <= NOT i_rx_clk OR tb_end AFTER c_rx_clk_per/2;
+  i_rx_rst <= '0' AFTER c_rx_clk_per*170;
+
+  p_deserialize: PROCESS
+    VARIABLE bit_index     : NATURAL;
+    VARIABLE v_rx_out_data : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+    VARIABLE v_rx_out_ctrl : STD_LOGIC_VECTOR(c_usr_nof_bytes-1 DOWNTO 0);
+  BEGIN
+    WAIT UNTIL tr_rst = '0';
+    WAIT UNTIL i_rx_rst = '0' ;
+
+    -- Give TX time to serialize the first word.  
+    WAIT FOR c_rx_clk_per;
+
+    -- Wait for half of a serial clk period so data is stable when sampling
+    WAIT FOR c_line_clk_per/2;
+
+    WHILE tb_end='0' LOOP
+      -- Start deserializing. Deserialization will be completed on the next rising edge of rx_clk.
+      FOR byte IN 0 TO c_usr_nof_bytes-1 LOOP
+        -- Deserialize one byte
+        FOR bit IN 0 TO c_byte_w-1 LOOP
+          WAIT FOR c_line_clk_per; 
+          -- Read one bit and assemble the parallel data word
+          bit_index := byte*c_byte_w+bit;
+          v_rx_out_data(bit_index) := rx_in;
+        END LOOP;
+        -- Read the control bit from the line
+        WAIT FOR c_line_clk_per;
+        v_rx_out_ctrl(byte) := rx_in;
+        -- Ignore the unised tenth bit
+        WAIT FOR c_line_clk_per;
+      END LOOP;
+      
+      -- End of this deserialization cycle: the rx data word has been assembled.
+      rx_out_data <= v_rx_out_data;
+      rx_out_ctrl <= v_rx_out_ctrl;
+    END LOOP;
+
+  END PROCESS;
+
+END beh;

libraries/technology/transceiver/sim_transceiver_gx.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose:
+--   Drop-in simulation model for tech_transceiver_gx.vhd.
+-- Description:
+--   A fast serdes for simulation within tr_nonbonded.
+-- Remarks:
+--   None
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY sim_transceiver_gx IS 
+  GENERIC(
+    g_data_w     : NATURAL;
+    g_nof_gx     : NATURAL;
+    g_mbps       : NATURAL;
+    g_tx         : BOOLEAN;
+    g_rx         : BOOLEAN
+  );      
+  PORT(
+    tb_end       : IN  STD_LOGIC := '0';  -- in simulation stop internal clocks when tb_end='1' to support 'run -all'
+    
+    tr_clk       : IN  STD_LOGIC;
+
+    rx_clk       : OUT STD_LOGIC_VECTOR(g_nof_gx-1 DOWNTO 0);
+    rx_rst       : OUT STD_LOGIC_VECTOR(g_nof_gx-1 DOWNTO 0);
+    rx_sosi_arr  : OUT t_dp_sosi_arr(g_nof_gx-1 DOWNTO 0);
+    rx_siso_arr  : IN  t_dp_siso_arr(g_nof_gx-1 DOWNTO 0);
+
+    tx_clk       : OUT STD_LOGIC_VECTOR(g_nof_gx-1 DOWNTO 0);
+    tx_rst       : OUT STD_LOGIC_VECTOR(g_nof_gx-1 DOWNTO 0);
+    tx_sosi_arr  : IN  t_dp_sosi_arr(g_nof_gx-1 DOWNTO 0);
+    tx_siso_arr  : OUT t_dp_siso_arr(g_nof_gx-1 DOWNTO 0);
+   
+    --Serial I/O
+    rx_datain    : IN  STD_LOGIC_VECTOR(g_nof_gx-1 DOWNTO 0);
+    tx_dataout   : OUT STD_LOGIC_VECTOR(g_nof_gx-1 DOWNTO 0)
+  );
+
+END sim_transceiver_gx;
+
+ARCHITECTURE str OF sim_transceiver_gx IS
+
+  TYPE t_ctrl_2arr IS ARRAY(g_nof_gx-1 DOWNTO 0) OF STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+  
+  SIGNAL tr_rst      : STD_LOGIC;
+
+  SIGNAL i_tx_clk    : STD_LOGIC_VECTOR(g_nof_gx-1 DOWNTO 0);
+  SIGNAL tx_ready    : STD_LOGIC;
+
+  SIGNAL tx_in_ctrl  : t_ctrl_2arr;
+  SIGNAL rx_out_ctrl : t_ctrl_2arr;
+
+BEGIN
+
+  tx_clk <= i_tx_clk;
+
+  p_tx_rdy : PROCESS
+    VARIABLE v_tx_clk_cnt : NATURAL := 0;
+  BEGIN
+    tx_ready <= '0';
+    WAIT FOR 1084.8 ns;              -- Time until tx_rst (in tr_clk domain) is deasserted: tx init done
+    WHILE v_tx_clk_cnt < 1000 LOOP   -- 1000 tx clk cycles until alignment is completed
+      WAIT UNTIL rising_edge(i_tx_clk(0));
+      v_tx_clk_cnt := v_tx_clk_cnt + 1;
+      tx_ready <= '1';
+    END LOOP;
+    WAIT;
+  END PROCESS;
+
+  gen_sim: FOR i IN 0 to g_nof_gx-1 GENERATE
+    gen_tx : IF g_tx = TRUE GENERATE
+      tx_siso_arr(i).ready <= tx_ready;
+      tx_siso_arr(i).xon   <= tx_ready;
+
+      gen_fanout: FOR j IN g_data_w/c_byte_w-1 DOWNTO 0 GENERATE
+        tx_in_ctrl(i)(j) <= tx_sosi_arr(i).valid;
+      END GENERATE;
+
+      u_ser: ENTITY work.sim_transceiver_serializer
+      GENERIC MAP (
+        g_data_w     => g_data_w,
+        g_line_rate  => g_mbps
+      )
+      PORT MAP (
+        tb_end       => tb_end,
+        
+        tr_clk       => tr_clk,  
+        tr_rst       => tr_rst,
+         
+        tx_clk       => i_tx_clk(i),   
+        tx_rst       => tx_rst(i),    
+    
+        tx_in_data   => tx_sosi_arr(i).data(g_data_w-1 DOWNTO 0),
+        tx_in_ctrl   => tx_in_ctrl(i),
+    
+        tx_out       => tx_dataout(i)
+      );
+    END GENERATE;
+
+    gen_rx : IF g_rx = TRUE GENERATE   
+      u_des: ENTITY work.sim_transceiver_deserializer 
+      GENERIC MAP (
+        g_data_w     => g_data_w,
+        g_line_rate  => g_mbps
+      )
+      PORT MAP (
+        tb_end       => tb_end,
+        
+        tr_clk       => tr_clk,  
+        tr_rst       => tr_rst,
+         
+        rx_clk       => rx_clk(i),   
+        rx_rst       => rx_rst(i),    
+    
+        rx_out_data  => rx_sosi_arr(i).data(g_data_w-1 DOWNTO 0),
+        rx_out_ctrl  => rx_out_ctrl(i),
+    
+        rx_in        => rx_datain(i)
+      );
+    END GENERATE;
+
+    rx_sosi_arr(i).valid <= andv(rx_out_ctrl(i));
+
+  END GENERATE;
+
+  u_areset_tr_rst : ENTITY common_lib.common_areset
+  GENERIC MAP(
+    g_rst_level => '1'
+  )
+  PORT MAP(
+    clk     => tr_clk,
+    in_rst  => '0',
+    out_rst => tr_rst
+  );  
+
+END str;
+

libraries/technology/transceiver/sim_transceiver_serializer.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose:
+--   Basic serializer model for fast transceiver simulation
+-- Description:
+--   This model can be connected to the transmitter entity serial 
+--   transmitter output in simulation. As all serializers in the simualation are
+--   simultaneously released from reset and share the same transceiver
+--   reference clock, we don't need to worry about synchronization and can
+--   simply assign one or more bits per serial group as validity indicator. The most 
+--   straightforward is to mimic 10/8 encoding for as far as data rates and clock 
+--   ratios are concerned (not the encoding itself):
+--   * User data rate = (8/10)*line data rate
+--   * User clock frequency = User data rate / user data width
+--   * Serial data block size = 10 bits [9..0] LSb sent first
+--     *  [9] = Unused, '0'., indiced by 'x'.
+--     *  [8] = Control bit.
+--     *  [7..0] = Data
+--   * Word/byte alignment is not required because reference clk and rst are global in
+--     simulation: what gets transmitted first is received first.
+--   
+--  The following diagram shows the serialization of the 32-bit word 0x2. The grid of dots
+--  indicates the bit resolution. Note the 1 serial cycle of delay before the first bit
+--  is put on the line.
+--
+--         . _______________________________________ . . . . . . . . . . . . . . . . . . . . .
+-- tx_clk  _|. . . . . . . . . . . . . . . . . . . .|_________________________________________
+--         _ . . _ . . . . . . _ . . . . . . . . . _ . . . . . . . . . _ . . . . . . . . . _ .        
+-- tx_out  .|___|.|___________|.|_________________|.|_________________|.|_________________|.|_
+-- 
+--         c x 0 1 2 3 4 5 6 7 c x 0 1 2 3 4 5 6 7 c x 0 1 2 3 4 5 6 7 c x 0 1 2 3 4 5 6 7 c x
+--            |<----- Byte 0 ---->|<----- Byte 1 ---->|<----- Byte 2 ---->|<----- Byte 3 ---->|
+--
+-- Remarks:
+--   . Requirements:
+--     . All serializers in the simualation should be simultaneously released from 
+--       reset and have to share the same transceiver reference clock.
+--   . This serializer is used in the tr_nonbonded module as a behavioural model 
+--     inside phy_gx.vhd.
+
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY sim_transceiver_serializer IS 
+  GENERIC(
+    g_data_w     : NATURAL := 32;
+    g_line_rate  : NATURAL := 6250 -- In Mbps. This yields tx_clk period = ((8/10)*line_rate)/g_data_w
+  );      
+  PORT(
+    tb_end       : IN  STD_LOGIC := '0';  -- in simulation stop internal clocks when tb_end='1' to support 'run -all'
+    
+    tr_clk       : IN  STD_LOGIC;
+    tr_rst       : IN  STD_LOGIC;
+
+    tx_clk       : OUT STD_LOGIC;
+    tx_rst       : OUT STD_LOGIC;
+
+    tx_in_data   : IN  STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+    tx_in_ctrl   : IN  STD_LOGIC_VECTOR(g_data_w/c_byte_w-1 DOWNTO 0);
+
+    tx_out       : OUT STD_LOGIC
+  );
+
+END sim_transceiver_serializer;
+
+
+ARCHITECTURE beh OF sim_transceiver_serializer IS
+
+  CONSTANT c_line_clk_per     : TIME    := 1000000 ps /g_line_rate; --e.g. 160 ps line clk period for 6250 Mbps
+  CONSTANT c_usr_nof_bytes    : NATURAL := g_data_w / c_byte_w;
+  CONSTANT c_tx_clk_per       : TIME    := c_line_clk_per * ( (g_data_w*10)/8 );
+
+  SIGNAL i_tx_clk             : STD_LOGIC := '1';
+  SIGNAL i_tx_rst             : STD_LOGIC := '1';
+
+BEGIN
+ 
+  tx_clk   <= i_tx_clk;
+  tx_rst   <= i_tx_rst;
+  i_tx_clk <= NOT i_tx_clk OR tb_end AFTER c_tx_clk_per/2;
+  i_tx_rst <= '0' AFTER c_tx_clk_per*170;
+
+  p_serialize: PROCESS
+    VARIABLE bit_index : NATURAL;
+  BEGIN
+    tx_out <= '0';
+    WAIT UNTIL tr_rst = '0';
+    WAIT UNTIL i_tx_rst = '0' ;
+
+    -- Deserializer waits for c_line_clk_per/2 
+    WAIT FOR c_line_clk_per;
+
+    WHILE tb_end='0' LOOP
+      -- New serialization cycle
+      FOR byte IN 0 TO c_usr_nof_bytes-1 LOOP
+        -- Put a data byte on the line
+        FOR bit IN 0 TO c_byte_w-1 LOOP
+          -- Put a data bit on the line
+          tx_out <= tx_in_data(byte*c_byte_w+bit);
+          -- Wait for one line clk period. The sum of all of these line clock cycles automatically 
+          -- creates the correct tx_clk period - for example if g_data_w = 32 and g_line_rate = 5000,
+          -- 40 (32 bits incl. 10/8 overhead) bits have to be serialized, one bit per 200 ps period.
+          -- These settings would yield a tx_clk period of 40*200 ps = 8 ns (125 MHz).
+          WAIT FOR c_line_clk_per;
+        END LOOP;
+        -- Put the control bit on the line for each byte
+        tx_out <= tx_in_ctrl(byte);
+        -- Wait for one line clk period
+        WAIT FOR c_line_clk_per;
+        -- Put the unused tenth bit = '0' on the line
+        tx_out <= '0';
+        -- Wait for one line clk period
+        WAIT FOR c_line_clk_per;
+      END LOOP;
+    END LOOP;
+
+  END PROCESS;
+
+END beh;