Support synchronous reset tree via g_tree_len, to ease reset timing closure.

libraries/base/common/src/vhdl/common_areset.vhd

@@ -23,7 +23,8 @@
 -- Purpose: Immediately apply reset and synchronously release it at rising clk
 -- Description:
 --   When in_rst gets asserted, then the out_rst gets asserted immediately (= asynchronous reset apply).
---   When in_rst gets de-assered, then out_rst gets de-asserted after g_delay_len cycles (= synchronous reset release).
+--   When in_rst gets de-assered, then out_rst gets de-asserted after g_delay_len cycles (= synchronous
+--   reset release) + g_tree_len cycles (synchronous reset tree).
 --
 --   The in_rst assert level is set by g_in_rst_level.
 --   The out_rst assert level is set by c_out_rst_level = g_rst_level.
@@ -40,7 +41,8 @@ entity common_areset is
     g_in_rst_level : std_logic := '1';  -- = in_rst level
     g_rst_level    : std_logic := '1';  -- = out_rst level (keep original generic
                                         --   name for backward compatibility)
-    g_delay_len    : natural   := c_meta_delay_len
+    g_delay_len    : natural := c_meta_delay_len;
+    g_tree_len     : natural := c_tree_delay_len
   );
   port (
     in_rst    : in  std_logic;
@@ -50,13 +52,18 @@ entity common_areset is
 end;
 
 architecture str of common_areset is
+  constant c_out_rst_value   : natural   := to_int(g_rst_level);
   constant c_out_rst_level   : std_logic := g_rst_level;
   constant c_out_rst_level_n : std_logic := not g_rst_level;
 
   signal i_rst               : std_logic;
+  signal o_rst               : std_logic;
 begin
   i_rst <= in_rst when g_in_rst_level = '1' else not in_rst;
 
+  -- 2009
+  -- Capture asynchronous reset assertion, to also support i_rst when there is
+  -- no clk.
   u_async : entity work.common_async
   generic map (
     g_rst_level => c_out_rst_level,
@@ -66,6 +73,24 @@ begin
     rst  => i_rst,
     clk  => clk,
     din  => c_out_rst_level_n,
-    dout => out_rst
+    dout => o_rst
+  );
+
+  -- 2024
+  -- Pass on synchronized reset with sufficient g_tree_len to ease timing
+  -- closure by FF duplication in out_rst tree. Keep rst = '0' to break
+  -- combinatorial path with in_rst to ease timing closure in the reset tree
+  -- network. Use g_tree_len = 0 for wire out_rst <= 0_rst, so no reset tree
+  -- as in 2009.
+  u_pipe : entity work.common_pipeline_sl
+  generic map (
+    g_pipeline    => g_tree_len,
+    g_reset_value => c_out_rst_value
+  )
+  port map (
+    rst     => '0',
+    clk     => clk,
+    in_dat  => o_rst,
+    out_dat => out_rst
   );
 end str;