Use array postfix '_arr' for mdio_m* port signals.

libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd

@@ -75,9 +75,9 @@ ENTITY mms_tr_xaui IS
       
     -- MDIO interface
     mdio_rst                : OUT STD_LOGIC;
-    mdio_mdc                : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);       
-    mdio_mdat_in            : IN  STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>'0');
-    mdio_mdat_oen           : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0)
+    mdio_mdc_arr            : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);       
+    mdio_mdat_in_arr        : IN  STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>'0');
+    mdio_mdat_oen_arr       : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0)
   );
 END mms_tr_xaui;
 
@@ -168,9 +168,9 @@ BEGIN
     
     -- MDIO interface
     mdio_rst           => mdio_rst,
-    mdio_mdc           => mdio_mdc,
-    mdio_mdat_in       => mdio_mdat_in,
-    mdio_mdat_oen      => mdio_mdat_oen
+    mdio_mdc_arr       => mdio_mdc_arr,
+    mdio_mdat_in_arr   => mdio_mdat_in_arr,
+    mdio_mdat_oen_arr  => mdio_mdat_oen_arr
   );
 
   u_mms_diagnostics: ENTITY diagnostics_lib.mms_diagnostics

libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd

@@ -81,9 +81,9 @@ ENTITY tr_xaui IS
 
     -- MDIO interface
     mdio_rst                : OUT STD_LOGIC;
-    mdio_mdc                : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);       
-    mdio_mdat_in            : IN  STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>'0');
-    mdio_mdat_oen           : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0)
+    mdio_mdc_arr            : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);       
+    mdio_mdat_in_arr        : IN  STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>'0');
+    mdio_mdat_oen_arr       : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0)
   );
 END tr_xaui;
 
@@ -223,22 +223,22 @@ BEGIN
     )
     PORT MAP (
       -- Transceiver PLL reference clock   
-      tr_clk          => tr_clk,
-      tr_rst          => tr_rst,
+      tr_clk            => tr_clk,
+      tr_rst            => tr_rst,
     
       -- MM clock for register of optional MDIO master
-      mm_clk          => mm_clk,
-      mm_rst          => mm_rst,
+      mm_clk            => mm_clk,
+      mm_rst            => mm_rst,
     
       -- MDIO master = mm slave
-      mdio_mosi_arr   => mdio_mosi_arr,
-      mdio_miso_arr   => mdio_miso_arr,
+      mdio_mosi_arr     => mdio_mosi_arr,
+      mdio_miso_arr     => mdio_miso_arr,
     
       -- MDIO External clock and serial data.
-      mdio_rst        => mdio_rst,
-      mdio_mdc        => mdio_mdc,
-      mdio_mdat_in    => mdio_mdat_in,
-      mdio_mdat_oen   => mdio_mdat_oen
+      mdio_rst          => mdio_rst,
+      mdio_mdc_arr      => mdio_mdc_arr,
+      mdio_mdat_in_arr  => mdio_mdat_in_arr,
+      mdio_mdat_oen_arr => mdio_mdat_oen_arr
     );
   END GENERATE;
       

libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd

@@ -48,9 +48,9 @@ ENTITY tr_xaui_mdio IS
 
     -- MDIO External clock and serial data.
     mdio_rst                : OUT STD_LOGIC;
-    mdio_mdc                : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);       
-    mdio_mdat_in            : IN  STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>'0');
-    mdio_mdat_oen           : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0)
+    mdio_mdc_arr            : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);       
+    mdio_mdat_in_arr        : IN  STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>'0');
+    mdio_mdat_oen_arr       : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0)
   );
 END tr_xaui_mdio;
 
@@ -115,9 +115,9 @@ BEGIN
       rx_dat            => mdio_rx_dat(i),
     
       -- External clock and serial data
-      mdc               => mdio_mdc(i),
-      mdat_in           => mdio_mdat_in(i),
-      mdat_oen          => mdio_mdat_oen(i)
+      mdc               => mdio_mdc_arr(i),
+      mdat_in           => mdio_mdat_in_arr(i),
+      mdat_oen          => mdio_mdat_oen_arr(i)
     );
 
     -- MM port